Cryogenic Electronic Interfaces for Quantum Computers

Our  research on cryo-CMOS interfaces for quantum computing is organized in a few main themes, as explained in the following.

Cryo-CMOS modelling

The aim is to characterize devices from several CMOS technologies over a wide range of cryogenic temperatures (30 mK – 77 K) and develop models suitable for analog and digital circuit design over such range. Currently, we have already fabricated and characterized test structures in 0.16-μm CMOS and 40-nm CMOS and, in collaboration with Prof. A. Valdimirescu (UC Berkeley/isep), we have been able to build a device model that is compatible with standard integrated-circuit design tools and that has been used for successfully designing complex analog circuits.

Testchip with cryo-CMOS device test structures being tested in our cryogenic probe station

Controllers for quantum processors

Designing a quantum computer will require co-optimizing the classical controller and the quantum processor. We are engineering such system and deriving the specifications for the electronics, by both analyzing and simulating the physics of the quantum devices and by experimenting on existing quantum processors. Today, we are already able to derive a complete set of specifications and trade-offs for the electronic controller for single-electron spin qubits.

Cryo-CMOS circuits and systems

Capitalizing on our broad research experience on RF/analog/mixed-signal CMOS electronics at room temperature, thegroup is developing cryogenic circuit blocks to be integrated in the controller, including signal multiplexers and demultiplexers, amplifiers, analog-to-digital and digital-to-analog converters. We will explore the trade-offs between operating temperature, available refrigeration power and functionality, that could result in some components working at 4 K or higher temperatures and others at mK temperatures, possibly on the same die with the qubits. We have already been able to demonstrate the functionality of a low-noise amplifier in a standard CMOS technology operating at 4 K.

PCB for qubit read-out (QuRo) comprising a cryo-CMOS low-noise amplifier (LNA) bonded on the board and an off-the-shelf FPGA for further processing the LNA output. The full board is functional down to 4 K.

The PCB with Cryo-CMOS components is being debugged at room temperature. The board is mounted at the end of a dip stick to allow immersion in liquid Helium for cryogenic testing.


Cryogenic temperature sensors & references

The objective is the development of supporting electronics for the controller, such as on-chip temperature sensors, references (current, voltage, frequency) and supply regulators, which are required for proper operation of any circuit block at cryogenic temperature. Having characterized the cryogenic behavior of standard CMOS devices employed in integrated voltage references and temperature sensors, we are currently investigating how to use those devices for references and sensors operating over a wide temperature range from 300 K down to 4 K and below.

Cryogenic digital circuits

Building a computing device such as a quantum computer requires a large amount of classical logic, for instance to provide hardware support for the quantum microarchitecture and to process the digital signals from and to the data convertrs directly connected to the quantum processor. Our objective is to exploit the specific advanatges of cryo-CMOS devices, such as the extreme low leakage and the high-subthreshold slope, to design cryogenic logic with superior performance.