Rajendra Bishnoi

Rajendra Bishnoi is currently an Assistant Professor with the Computer Engineering (CE) Laboratory group, Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Delft University of Technology (TU-Delft).

He received the Ph.D. degree in computer science from the Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany, in 2017. Before joining TU-Delft, he was a Post-doctoral researcher with the MRAM Group, Chair of Dependable Nano Computing, KIT, working on emerging technologies such as Spin Transfer Torque (STT), Spin Orbit Torque (SOT) technologies and Printed Electronics (inorganic). From 2006 to 2012, he was a Design Engineer with Freescale (now become NXP), where he was a part of the Technical Solution Group working on memories and SoC design flow.

He has authored/co-authored over 80 publications in major Journals and Conference proceedings as well as holds six pending/grated EU patents. His current research is focused on neuromorphic computing using emerging technologies based on computation-in-memory architectures targeting edge applications. He was a recipient of the European Design & Automation Association (EDAA) outstanding dissertation award for the year 2017 as well as the best Ph.D. Forum award at the DATE conference venue in 2016. He was a guest editor for “Frontiers in Neuroscience” Journal in 2022 and served as a Technical Program Committee Member for DATE-2021, DATE-2022 and ATS-2021 conferences. He is currently editorial board member for “Elsevier” Journal for “Memories – Material, Devices, Circuit and System”.

My current research is to design ultra-low power neuromorphic processors targeting healthcare edge applications. We employ computation-in-memory architectures using emerging technologies such as Resistive Random Access Memories (RRAM), Ferroelectric Field-effect Transistor (FeFET), Spin Transfer Torque (STT) as well as conventional SRAM. We develop novel bit-cell designs for the crossbar array as well as other energy-efficient analog circuit components such as Analog-to-Digital Converter (ADC) for the implementation of Spiking Neural Networks (SNN) and Artificial Neural Networks. We realize these innovative analog/mixed-signal designs which has important brain features such as asynchronous execution, adaptability in learning, sparse computation, and error resiliency. Additionally, we also use hardware-aware novel mapping techniques considering device-level non-idealities and efficient training processes (hardware-algorithm co-design) in order to improve the energy efficiency of the overall system.

During the course of the research projects, we have done following tape-outs:

  1. Developed a Computation-in-Memory (CIM) architecture using Ring-Oscillator based ADC for Edge AI applications. We propose a novel biasing scheme to obtain a linear activation function by virtually fixing the difference of select-line and bit-line to a constant voltage with precise inter-matching design techniques for accurate analog-to-digital conversions. Additionally, a new self-timed path technique is integrated to address the impact of variations as well as wire-delay mismatch by regulating the duration of the analog-to-digital conversion in each cycle.
  2. Designed a unique bit-cell and a constant current source based computation unit for a Computation-in-Memory (CIM) architecture. The design can operate at a very low current (~100nA), which is independent of the input values.


SELF Delft-AI Lab (Aug’22 to July’27): This project is a part of the TU-Delft AI labs and Talent programme. SELF project targets the design, development and prototyping ultra-low power smart computing engines for edge applications (epilepsy early detection as an use case).  The computing engine is based-on computation-in-memory architecture (beyond traditional Von-Neumann) making use of memristor devices (suitable for brain inspired computing),  combined with new biological inspired learning algorithms and power aware efficient mapping methods. For more information, visit following link:


NeuroKIt2e (Jun’23 to May’26): It is a part of the European Union KDT-JU (Key Digital Technologies Joint Undertaking) program  The goal of this project is to propose a new open-source Deep Learning Platform for Embedded Hardware. Our role in this project is to model, develop and optimize the computation-in-memory based accelerators for a Neural Network applications.

DAIS (Jun’23 to May’26): Distributed Artificial Intelligent Systems (DAIS) project is a part of the European Union ECSEL program. The main objective of this project is to develop hardware and software Edge AI components that are self-organizing, private by design and energy-efficient. Our role in this project is to develop new low-power hardware architectures that can enable the deployment of AI at the edge.

Supervising PhDs

  • Abhairaj Singh, Low power and reliable Computation-in-memory hardware design, started on Aug’19.
  • Sumit Diware, Computation-in-memory based microarchitecture for edge AI, started on Jun’20.
  • Amin Yaldagard, Circuit Design for RRAM-based Computation-in-memory, started on Sept’2022.
  • Alirea Raisiardali, AI architecture for healthcare applications, started on Oct’2022 (Jointly supervising with Dr. Dante Muratore from ME/BE)
  • Yash Biyani, Circuit Design for FeFET-based Computation-in-memory, started on Nov’2022.

MSc Students (Current)

  • Douwe Brinkhorst
  • Lucas Huijbregts
  • Yingzhou Dong

MSc Students (Graduated)

  • David Veselka
  • Sudeshna Dash
  • Koteswararao Chilakala
  • Varun Sudhakar
  • Yash Biyani