Design for Reliability (DfR) of 3D Integration Schemes for Quantum Computers
Quantum Computers are poised to revolutionize computing by providing exponentially faster processing power than classical computers for certain types of problems. However, current quantum computers are limited by their small size and the difficulty of scaling up the number of qubits. To overcome this challenge, 3D Integration of Quantum Computers has emerged as a promising approach, allowing for more qubits to be packed into a smaller footprint.
Reliability testing of 3D Integrated Flip-Chip Assemblies is essential to ensure the long-term performance of these complex systems. The high density of components and the advanced superconducting interconnect technologies used in our packages can create unique reliability challenges, such as thermal stresses, mechanical fatigue, and interfacial reliability issues. Without adequate reliability testing, these packages may fail prematurely in the field, leading to costly recalls, repairs, or replacements.
Reliability testing can help identify and address potential failure mechanisms, validate the design assumptions, and provide assurance that the package will meet the specified performance and durability requirements. Moreover, as the demand for smaller, faster, and more powerful electronic devices continues to grow, the importance of reliable 3D packaging technologies will only increase, making reliability testing an indispensable part of the development and manufacturing process.
- Investigate the design and fabrication of 3D-Integration schemes with an active interposer.
- Refine novel integration techniques to overcome the challenges of 3D integration of quantum computers, such as thermal management and interconnect reliability.
- Characterize the performance and reliability of Interposer Layers, TSVs, and Microbumps, including the impact of fabrication and integration processes on device performance.
To achieve these objectives, we will use a combination of experimental and computational techniques. We will simulate the impact of fabrication and integration processes on CTE mismatch, heat flux, and wafer-level stresses. We will also perform extensive electrical, RF, and thermal simulations before moving on to the fabrication phase where we will make 3D-Integrated Interposer prototypes at Kavli Nanolab and/or EKL using advanced fabrication techniques such as flip-chip bonding and throughsilicon vias. We will then perform extensive characterization of these devices, including measurements of superconductivity and extensive reliability testing.
- A better understanding of the challenges and opportunities of 3D integration of quantum computers.
- Novel integration techniques for 3D integration of quantum computers that can be applied to future generations of devices.
- A comprehensive characterization of 3D-integrated quantum computers, including their performance and reliability.
- Insights into the potential applications of 3D-integrated quantum computers and their impact on various industries.
In summary, this project aims to investigate the 3D integration of quantum computers, including the design and fabrication of prototypes, development of novel integration techniques, and characterization of device performance and reliability. This project's outcomes will advance our understanding of 3D-integrated quantum computers and lay the groundwork for the development of future quantum computing technologies.
 R. Ishihara et al., "3D Integration Technology for Quantum Computer based on Diamond Spin Qubits," 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 14.5.1-14.5.4, doi: 10.1109/IEDM19574.2021.9720552.
 Shen, WW., Chen, KN. Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV). Nanoscale Res Lett 12, 56 (2017). doi.org/10.1186/s11671-017-1831-4
 Ishii, T., Aoyama, S. Novel micro-bump fabrication for flip-chip bonding. J. Electron. Mater. 33, L21– L23 (2004). doi.org/10.1007/s11664-004-0172-0
 Y. Li, A. M. Gheytaghi, M. Trifunovic, Y. Xu, G. Q. Zhang, and R. Ishihara, “Wafer-level direct bonding of optimized superconducting nbn for 3d chip integration,” Physica C: Superconductivity and its Applications, vol. 582, p. 1353823, 2021. [Online]. Available: www.sciencedirect.com/science/article/pii/S092145342100006X9
 J. H. Lau and T. G. Yue, “Effects of tsvs (through-silicon vias) on thermal performances of 3d ic integration system-in-package (sip),” Microelectron. Reliab., vol. 52, pp. 2660–2669, 2012