Koen Bertels

I am the head of the Computer Engineering Laboratory and head of the  Quantum Engineering department.  I currently focus on Quantum Computing and more specifically on the overall system design and architecture aspects.  In this respect, I am a principal investigator in Qutech where I collaborate  with experimental physicists on building prototype quantum processors.

My other research interests span two of the three research pillars of the Lab, namely Multi and Many-core architectures and Electronic System Level Design.  More specifically, I was responsible for the Delft Workbench project that aims to provide semi-automatic support for designing heterogeneous multicore platforms where reconfigurable technology offers plenty of possibilities to generate application specific hardware at runtime.  An overview of relevant publications on various topics related to heterogeneous multicore computing can be found on my research page.

I also started a company, together with colleagues from the CE lab and  Wayne Luk from Imperial College, called BlueBee and that provides a cloud service for genome sequencing.  Bluebee received 10 Mio € venture capital in 2016. More information can be found on the BlueBee website.

If you are looking for a time slot to meet me, please look at my agenda and propose a time slot.

Current research on Quantum Computing

I am a principal investigator in the Qutech research center and responsible for the quantum architecture and system design aspects. This involves the following topics:

  1. The overall heterogeneous micro-architecture of a quantum compuer
  2. The architecture of the qubit plane
  3. Classical (and thus limited) simulation of a quantum computer
  4. Compiling for quantum

Past research

My past research was driven by the need to make heterogeneous multicore processors more easily programmable and to fully exploit the available hardware in a way which is as transparent as possible for the developer. However, the times where developers do not need to know any low level detail of the processor architecture are over.  Especially when reconfigurable computing components such as FPGA blades are available, this becomes especially challenging as it assumes hardware design expertise to be able to use them.  The inclusion of such components is increasingly popular, both for embedded systems as well as for supercomputing.  Examples of current day platforms are : the Zynq from Xilinx or IBM's Power 8 with CAPI interfaces to plug in FPGA blades.  Another nice example was the Convey supercomputer which was bought by Micro.

The main challenge is to exploit in an efficient way the different computing elements and how the hardware should evolve with the specific needs of the application which is being executed.

Relevant publications are : 

  1. On hardware-software co-design

    1. K.L.M. Bertels, V.M. Sima, Y.D. Yankova, G.K. Kuzmanov, W. Luk, G. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada,D. Sciuto, A. Michelotti, hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms (October 2010), IEEE Micro, volume 30, issue 5 , Special Issue on European Multicore Processing Projects

  2. On placement of tasks on the reconfigurable area

    1. Y. Lu, T. Marconi, K.L.M. Bertels, G.N. Gaydadjiev, Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems http://ce-publications.et.tudelft.nl/publications/362_online_task_scheduling_for_the_fpgabased_partially_reconfig.pdf (March 2009), 5th International Workshop on Applied Reconfigurable Computing: Architectures, Tools and Applications (ARC 2009), 16-18 March 2009, Karlsruhe, Germany
    2. T. Marconi, Y. Lu, K.L.M. Bertels, G.N. Gaydadjiev, Intelligent Merging Online Task Placement Algorithm for Partial Reconfigurable Systems http://ce-publications.et.tudelft.nl/publications/492_intelligent_merging_online_task_placement_algorithm_for_part.pdf (March 2008), Design, Automation and Test in Europe (DATE 2008), 10-14 March 2008, Munich, Germany
    3. Y. Lu, T. Marconi, K.L.M. Bertels, G.N. Gaydadjiev, A Communication Aware Online Task Scheduling Algorithm for FPGA-based Partially Reconfigurable Systems http://ce-publications.et.tudelft.nl/publications/189_a_communication_aware_online_task_scheduling_algorithm_for_f.pdf (May 2010), 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), 2-4 May 2010, Charlotte, USA
    4. Y. Lu, K.L.M. Bertels, G.N. Gaydadjiev, Efficient hardware task reuse and interrupt handling mechanisms for FPGA-based partially reconfigurable systems (December 2010), International Conference on Field-Programmable Technology (FPT 2010), 8-10 December 2010, Beijing, China

  3. On compiler related issues for heterogeneous multicore

    1. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Compiling for the Molen Programming Paradigm http://ce-publications.et.tudelft.nl/publications/1501_compiling_for_the_molen_programming_paradigm.pdf(September 2003), 13th International Conference on Field Programmable Logic and Applications (FPL 2003), 1-3 September 2003, Lisbon, Portugal
    2. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Compiler-driven FPGA-area Allocation for Reconfigurable Computing http://ce-publications.et.tudelft.nl/publications/758_compilerdriven_fpgaarea_allocation_for_reconfigurable_comp.pdf (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany 
    3. E. Moscu Panainte, K.L.M. Bertels, S. Vassiliadis, Compiler-driven FPGA-area Allocation for Reconfigurable Computing http://ce-publications.et.tudelft.nl/publications/758_compilerdriven_fpgaarea_allocation_for_reconfigurable_comp.pdf (March 2006), Design, Automation and Test in Europe (DATE 2006), 6-10 March 2006, Munich, Germany
    4. R. Nane, V.M. Sima, C. Pilato, J. Choi, B Fort, A Canis, Y.T. Chen, H Hsiao, S Brown, F. Ferrandi, J Anderson,K.L.M. Bertels, A Survey and Evaluation of FPGA High-Level Synthesis Tools http://ce-publications.et.tudelft.nl/publications/1524_a_survey_and_evaluation_of_fpga_highlevel_synthesis_tools.pdf (December 2015), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
    5. R. Nane, V.M. Sima, B Olivier, R.J. Meeuws, Y.D. Yankova, K.L.M. Bertels, DWARV 2.0: A CoSy-based C-to-VHDL Hardware Compiler http://ce-publications.et.tudelft.nl/publications/600_dwarv_20_a_cosybased_ctovhdl_hardware_compiler.pdf (August 2012), 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), 29-31 August 2012, Oslo, Norway

  4. On instruction set extensions

    1. C. Galuzzi, K.L.M. Bertels, S. Vassiliadis, A linear complexity algorithm for the automatic generation of convex multiple input multiple output instructions (July 2008), International Journal of Electronics (IJE)
    2. C. Galuzzi, K.L.M. Bertels, S. Vassiliadis, A Linear Complexity Algorithm for the Generation of Multiple Inputs Single Output Instructions of Variable Size http://ce-publications.et.tudelft.nl/publications/587_a_linear_complexity_algorithm_for_the_generation_of_multiple.pdf (July 2007), 7th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2007), 16-19 July 2007, Samos, Greece

  5. On data-driven profiling of applications

    1. S.A. Ostadzadeh, R.J. Meeuws, C. Galuzzi, K.L.M. Bertels, QUAD - A Memory Access Pattern Analyser http://ce-publications.et.tudelft.nl/publications/207_quad__a_memory_access_pattern_analyser.pdf(March 2010), 6th International Symposium on Applied Reconfigurable Computing (ARC 2010), 17-19 March 2010, Bangkok, Thailand
    2. I. Ashraf, K.L.M. Bertels, N. Khammassi, J.C. Le Lann, Communication-aware Parallelization Strategies for High Performance Applications http://ce-publications.et.tudelft.nl/publications/1487_communicationaware_parallelization_strategies_for_high_per.pdf (July 2015), IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 08-10 July 2015, Montpellier, France
    3. I. Ashraf, V.M. Sima, K.L.M. Bertels, Intra-Application Data-Communication Characterization http://ce-publications.et.tudelft.nl/publications/1488_intraapplication_datacommunication_characterization.pdf (July 2015), 1st International Workshop on Communication Architectures at Extreme Scale (ExaComm 2015), 16 July 2015, Frankfurt, Germany
    4. I. Ashraf, S.A. Ostadzadeh, R.J. Meeuws, K.L.M. Bertels, Communication-aware HW/SW Co-design for Heterogeneous Multicore Platforms http://ce-publications.et.tudelft.nl/publications/143_communicationaware_hwsw_codesign_for_heterogeneous_multic.pdf (July 2012), 10th International Workshop on Dynamic Analysis (WODA 2012), 15 July 2012, Minneapolis, USA

  6. On runtime for reconfigurable processors

    1. V.M. Sima, K.L.M. Bertels, Runtime decision of hardware or software execution on a heterogeneous reconfigurable platform http://ce-publications.et.tudelft.nl/publications/343_runtime_decision_of_hardware_or_software_execution_on_a_hete.pdf (May 2009), 16th Reconfigurable Architectures Workshop (RAW 2009), 25-26 May 2009, Rome, Italy
    2. G. Mariani, V.M. Sima, G. Palermo, V. Zaccaria, C. Silvano, K.L.M. Bertels, Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures http://ce-publications.et.tudelft.nl/publications/128_using_multiobjective_design_space_exploration_to_enable_run.pdf (March 2012),Design, Automation & Test in Europe Conference & Exhibition (DATE 2012), 12-16 March 2012, Dresden, Germany

  7. On bio-informatics acceleration

    1. L. Hasan, Z. Al-Ars, Z. Nawaz, K.L.M. Bertels, Hardware Implementation of the Smith-Waterman Algorithm Using Recursive Variable Expansion http://ce-publications.et.tudelft.nl/publications/512_hardware_implementation_of_the_smithwaterman_algorithm_usin.pdf (December 2008), 3rd IEEE International Design and Test Workshop (IDT 2008), 20-22 December 2008, Monastir, Tunisia
    2. Z. Nawaz, M. Nadeem, J. van Someren, K.L.M. Bertels, A parallel FPGA design of the Smith-Waterman traceback http://ce-publications.et.tudelft.nl/publications/220_a_parallel_fpga_design_of_the_smithwaterman_traceback.pdf (December 2010), International Conference on Field-Programmable Technology (FPT 2010), 8-10 December 2010, Beijing, China
    3. Z. Nawaz, M. Shabbir, Z. Al-Ars, K.L.M. Bertels, Acceleration of Smith-Waterman Using Recursive Variable Expansion http://ce-publications.et.tudelft.nl/publications/425_acceleration_of_smithwaterman_using_recursive_variable_expa.pdf (September 2008), 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2008), 3-5 September 2008, Parma, Italy
    4. E.J. Houtgast, V.M. Sima, K.L.M. Bertels, Z. Al-Ars, GPU-Accelerated BWA-MEM Genomic Mapping Algorithm Using Adaptive Load Balancing http://ce-publications.et.tudelft.nl/publications/1520_gpuaccelerated_bwamem_genomic_mapping_algorithm_using_ada.pdf (April 2016), 29th International Conference on Architecture of Computing Systems (ARCS 2016), 4-7 April 2016, Nuremberg, Germany

I was involved in the following projects : 

  1. Morpheus : This FP6 project created a silicon prototype of the Molen polymorphic processor where an ARM was combined with 3 different reconfigurable fabrics on one die.  Besides the processor architecture, we were involved in the programming tool chain.

  2. Hartes aimed to lay the foundation for a new holistic (end-to-end) approach for complex real-time embedded system design, with the latest algorithm exploration tools and reconfigurable hardware technologies. From the application point of view, the complexity of future multimedia devices is becoming too big to design monolithic processing platforms. This is where the hArtes approach with reconfigurable heterogeneous systems becomes vital. The proposed approach addressed, for the first time, optimal and rapid design of embedded systems from high-level descriptions, targeting a combination of embedded processors, digital signal processing and reconfigurable hardware. We developed modular and scalable hardware platforms that can be reused and re-targeted by the tool chain to produce optimized real-time embedded products. The results were evaluated using advanced audio and video systems that support next-generation communication and entertainment facilities, such as immersive audio and mobile video processing.
    The outcomes of the project were described in the following book published by Springer Verlag : Hardware/Software Co-Design for Heterogeneous Multicore Processing.
    A spin off company, BlueBee b.v., was created to further mature and market the technology developed in hArtes.

  3. SoftSoc : SoftSoC was a CATRENE project that aimed at solving the main SoC productivity bottleneck by providing Hardware Dependant Software (HDS) solutions to enable SoC designers to aggregate multiple HW IP with their associated HDS into efficient design. Delft worked with LIACS and Compaan Design on a tool flow that incorporated the DWARV hardware compiler and the Compaan design flow. The CE lab was the scientific and technical coordinator of the project as well as work package leader.

  4. SMECY envisionend that recently emerged multi-core technologies will rapidly develop to massively parallel computing environments which, due to improved performance, energy and cost properties, will extensively penetrate the embedded system industry in a few years. This will affect and shape the whole business landscape, e.g. semiconductor vendors need to be capable of offering advanced multi-core platforms to diverse application sectors, IP providers need to re-target existing and develop new solutions to be compatible with evolving multi-core platforms and the need of embedded system houses, in addition to product architecture adaptations and renewing their system, architecture, software and hardware development processes. The CE lab is involved in reliable computing, workload characterisation and virtualisation of different processor architectures.

  5. The iFEST project  (industrial Framework for Embedded Systems Tools) aims at specifying and developing an tool integration framework for HW/SW co-design of heterogeneous and multi-core embedded systems. The integration framework will permit tools to be readily replaced within the tool chain; thus dealing with issues such as tool obsolescence and tool lock-in. IFEST industrial case studies will validate the integration framework and tool chains for control and streaming applications. The CE lab is work package leader and responsible for the HW/SW co-design tools integration.

  6. The REFLECT project stands for Rendering FPGAs to Multi-Core Embedded Computing.  The REFLECT's approach intends to solve some of the problems when mapping efficiently computations to FPGA-based systems. In particular, the use of aspects and strategies will allow developers to try different design patterns and to achieve solutions design-guided by non-functional requirements. To the best of our knowledge, the REFLECT design flow is the first approach considering a systematic control of all the compilation stages and the first one to consider the relationship between non-functional requirements to different design patterns and optimizations, both specified in a domain-specific language, named LARA.The CE lab is work package leader and responsible for the DWARV hardware compiler which generates VHDL from the C-code which was augmented by aspects.

  7. EMC2‘Embedded Multi-Core systems for Mixed Criticality applications in dynamic and changeable real-time environments’ is an ARTEMIS Joint Undertaking project in the Innovation Pilot Programme ‘Computing platforms for embedded systems’ (AIPP5). Embedded systems are the key innovation driver to improve almost all mechatronic products with cheaper and even new functionalities. They support today’s information society as inter-system communication enabler. A major industrial challenge arises from the need to face cost efficient integration of different applications with different levels of safety and security on a single computing platform in an open context. EMC² finds solutions for dynamic adaptability in open systems, provides handling of mixed criticality applications under real-time conditions, scalability and utmost flexibility, full scale deployment and management of integrated tool chains, through the entire lifecycle. EMC² is a project of 99 partners of embedded industry and research from 19 European countries with an effort of about 800 person years and a total budget of about 100 million Euro.

Teaching

I currently teach the following courses : 

  1. Electronics for Quantum Computing : the course focuses on the clasical control logic for quantum processors. The course is part of the Qutech academy.
  2. Embedded Systems Laboratory : Course in the ES Msc program in which the students have to develop an application on two different Embedded Platforms
  3. Operating Systems Course in the CE Msc program where students have to study one particular OS functionality and then implement a simplified version of it and experiment with some algorithmic alternatives.
  4. High Tech Start-up (Bsc program) The Bsc graduation project is based on the idea of brining technology to the market. In collaboration with researchers from the faculty, the students work on a prototype of the technology and write a business plan.
  5. High Tech Start-up (Msc program) This course familiarizes the student with the idea of starting a company.  It focuses on the necessary personal skills and organizational issues involved in doing that.

I taught the following courses over the last couple of years:

  1. Discrete Mathematics (Bachelor program) Introduction to set theory, Boolean algebras, graph theory, data structures, complexity analysis
  2. Programming in Java (Bachelor program) As this course is an introduction to programming using Java, it focuses on the basic object oriented programming notions. At the end of the course is student is capable of designing a small application having a GUI and multi tiered structured
  3. Computer Architecture I (Bachelor program) After introducing basic notions on Instruction Set Architectures, the most important computer arithmetic algorithms are presented.  Subsequent topics include processor design, memory caches, pipelining.
  4. Modern Computer Architectures (Msc program) Introduce state of the art notions in computer architecture such as superscalar computing, VLIW, multiprocessor, and some notions on multiprocessor and parallel systems are introduced

Students

My current PhD students are :

  1. Yana Yankova, DWARV - Automated hardware generation
  2. Valery Kritchallo, Approximate parallel computing
  3. Xiang Fu, micro-architecture for quantum computers
  4. LingLing Lao, mapping quantum circuits on the qubit plane
  5. Savvas Varsamopoulos, high-speed quantum decoders
  6. Dan Iorga, quantum plane architecture

Graduated PhD Students (12)

  1. Ph. Vanneste, Computer Science dept., Catholic University of Louvain. Advisor, Thesis: The use of Reverse Engineering in Novice Program Analysis, 1994,
  2. Ir.Luc Neuberg , Dept. Gestion de l'Entreprise, University of Namur. Advisor, Title: The analysis of financial markets using simulation, 1999
  3. E. Moscu-Panainte, Retargetable compiler for heterogeneous computing platforms, Delft University of Technology, 2007
  4. Carlo Galuzzi, Code Transformations for Application Specific Instruction Set generation, Delft University of Technology, 2009
  5. Behnaz Pourebrahimi, an economic framework for resource allocation in ad-hoc networks, Delft University of Technology, 2009
  6. Tariq Abdullah, adaptive Ad hoc grid computing, Delft University of Technology, 2010
  7. Zubair Nawaz, Recursive Variable Expansion: A transformation for Reconfigurable Computing, Delft University of Technology, 2011
  8. Kamana Sigdel, high level simulation of reconfigurable computing systems using Sesame and Kahn Process Networks, Delft University of Technology, 2011
  9. Mojtaba Sabeghi, Runtime support for multi-core architectures, Delft University of Technology, 2011
  10. Ozana Dragomir-Azevedo, K-loops: loop transformations for reconfigurable architectures, Delft University of Technology, 2011
  11. Lu Yi, Molen extensions for runtime and partial reconfiguration (with G. Gaydadjiev), Delft University of Technology, 2011
  12. Thomas Marconi, algorithms for runtime and partial reconfiguration (with G. Gaydadjiev), Delft University of Technology, 2011
  13. Vlad-Mihai Sima, Compiler assisted Runtime Adaptation, Delft University of Technology, January 2012
  14. Roel Meeuws, A quantitative model for early resource consumption prediction, Delft University of Technology, July 2012
  15. Arash Ostadzadeh, Characterising workloads for multi-core platforms, Delft University of Technology, December 2012
  16. Cuong Pham Quoc, Hybrid Interconnect and interprocessor communication co-supervised with Zaid Al-Ars
  17. Hamid Mushtaq, Runtime monitoring for fault tolerant computing co-supervised with Zaid Al-Ars
  18. Razvan Nane, Hardware templates for automated hardware generation: the Dwarv 2.0 C2VHDL compiler.
  19. Imram Ashraf, Data-communication driven mapping of sequential C-code on heterogeneous multicore platforms, April 2016

Koen Bertels