Item 1 of 1

Georgi Gaydadjiev

About

I hold the Chair in Computer Architecture at the QCE department. I am also honorary visiting professor at the Department of Computing of Imperial College since 2014. I am a member of the CogniGron Program Board at the University of Groningen.  

Previously, I held the Chair in Innovative Computer Architectures at the University of Groningen (August 2019 - June 2023) and the Chair in Computer Systems Engineering at Chalmers University of Technology in Sweden until 2015. I was a VP of Dataflow Software Engineering at Maxeler Technologies Ltd. in London (2014-2018) and in December 2017 I started Maxeler IoT-Labs BV in Delft and was its managing director until January 2020. Maxeler is now part of groq Inc.  

Between 2002 and 2011 I was a faculty member at the Computer Engineering section. I co-founded the master of science program in Computer Engineering and was its first coordinator. Prior to TU Delft, I spent close to 15 years in the computing industry in Bulgaria (Pravetz) and Netherlands (Pijnenburg Microelectronics & Software / CPS).

 

General and Program Chair:

  • 29th IEEE International Conference on Computer Design (ICCD'11) (General Chair)
  • 9th IEEE Symposium on Application Specific Processors (SASP'2011) (General co-Chair)
  • 28th IEEE International Conference on Computer Design (ICCD'10) (General Chair)
  • 8th IEEE Symposium on Application Specific Processors (SASP'2010) (Program co-Chair)
  • ACM International Conference on Computing Frontiers (CF'09) (Program Co-chair)
  • 27th IEEE International Conference on Computer Design (ICCD'09) (Program co-Chair)
  • 26th IEEE International Conference on Computer Design (ICCD'08) (Program Chair)
  • SAMOS VII: Embedded Computer Systems: Architectures, MOdeling, and Simulation (General chair)
  • XXV IEEE International Conference on Computer Design (ICCD'07) (Processor Architecture Track co-Chair)
  • SAMOS VI: Embedded Computer Systems: Architectures, MOdeling, and Simulation (Program chair)

Awards:

  • ACM/SIGARCH 24th International Conference on Supercomputing (ICS'10) Tsukuba, Japan, June 2010. Best paper award
  • Workshop in Information Security Theory and Practices 2007 (WiSTP'07), Heraklion, Greece, May 2007. Best student paper award
  • USENIX/SAGE Large Installation System Administration conference (LISA 2006), Washington DC, USA, Dec 2006. Best paper award
  • Prontomail Screen Phone P112, CES, Las Vegas, USA, 1999. Design & Engineering Showcase award

 

My research is/was funded by:

Research

My research interests include embedded systems design, computer architecture and micro-architecture, reconfigurable computing, hardware/ software co-design, VLSI design, and computer systems testing. Currently my research is on dynamic techniques to manage contemporary distributed memory systems for custom computing systems and heterogeneous multicores, application specific acceleration, and low overhead reliability techniques. All the above topics are in the context of the expected technology trends in the future when the quality of the available transistors is deteriorating while their quantity on a single chip keeps scaling up. These trends combined with the severe power dissipation constraints require novel, holistic hardware-software approaches and place new challenges to computer systems designers. A possible oversimplification of the problem is how to transform the available transistor quantity into affordable quality in respect to power dissipation per unit area and drastically reduce the required data center space. Needless to say that minimizing data movements at all system levels is a key to achieve the above goal. Getting serous about the data in rest and in processing is a key.

Projects

Current:

  • EXA2PRO, RIA H2020-FETHPC-2017, European Union, Contract number 801015, 2018-2021
  • SDK4ED, RIA , H2020-ICT-2017-1, European Union, Contract number 780572, 2018-2021
  • LEGaTO, RIA H2020-ICT-2017-1, European Union, Contract number 78068, 2017-2020
  • EuroEXA,  RIA H2020-FETHPC-2016, European Union, Contract number 754337, 2017-2021
  • VINEYARD, RIA H2020-ICT-2015, European Union, Contract number 687628, 2016-2019
  • AEGLE, RIA H2020-ICT-2014-1, European Union, Contract number 644906, 2015-2019
  • EXTRA, RIA H2020-FETHPC-2014, Contract number 671653, 2015-2018

Completed:

  • CloudLightning, FP7-ICT-2013-11, EU, Contract number 643946, 2015-2018
  • COSSIM, FP7-ICT-2013-11, EU, Contract number 644042, 2015-2018
  • QualiMaster, FP7-ICT-2013-11, EU, Contract number 619525, 2014–2017
  • SAVE, FP7-ICT-2013-10, EU, Contract number 610966, 2013–2016
  • HARNESS, FP7-ICT, EU, Contract number 318521, 2012-2015
  • EUROSERVER, IP FP7-ICT10, Computing Systems, European Union, Contract number 610456, 2013-2016
  • ProMSys: Programmable Multicore Systems, The Swedish research council VR, 2011-2014
  • EYE: Empowering Young Explorers, CSA FET-ICT-2013-C, EU, Contract number 619241, 2013-2015
  • on-Demand System Reliability (DeSyRe), STREP FP7-ICT7, Computing Systems, EU, Contract number 287611, 2011-2014
  • Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration (FASTER), STREP FP7-ICT7, Computing Systems, European Union, Contract number 287804, 2011-2014
  • ENabling technologies for a programmable many-CORE (ENCORE), STREP FP7-ICT4, Computing Systems, European Uni, Contract number 249059, 2010-2013
  • Google Inc. personal research award Configurable Accelerators for Google Applications, Jan 2009-2011
  • (Project coordinator of) Scalable Processor Architecture (SARC), Integrated project FP6, European Union, Contract number 27648, 2006-2010
  • Smart Cohlear Implants, SmartSIP, STW, 2008-2012
  • MISAT, Bsik subsidie, MicroNed, 2005-2009
  • High-Performance Architectures and Compilers (HiPEAC-2), Network of excellence of the European Union FP7, Contract number IST-217068, 2008-2012
  • High-Performance Architectures and Compilers (HiPEAC), Network of excellence of the EU FP6, Contract number IST-004408, 2003-2007
  • VALICHIP, Point-One, 2007-2009
  • hARTES, EU FP6 Priority 2.5.3 Embedded Systems, Integrated project, Contract number 035143, 2007-2010
  • Reliability techniques for implantable processors, Frame program 3TU with IMEC-NL (Samenwerking HOLST Center), 2007-2010
  • Scientific Multicore Vector processors, NUFFIC, (2x PhD students), 2007-2009
  • HiPEAC 1 and HiPEAC 2 (member of the Steering Committee)
  • Delfi-C3
  • SiMS / SINS
  • Smac-IT
  • RFID Guardian
  • MISAT

Publications

Teaching

  • I am teaching High Speed Digital Design for Embedded Systems (ET4 362)
  • I am teaching Hardware Fundamentals (CESE4005)
  • I taught Computer Architecture and Organization (ET2 608) 
  • I taught Introduction to Computer Engineering (ET4 246)
  • I taught Computer Systems Testing (ET4 076) 
  • I taught Elektronica (ET2 045ID) (digitale deel) 
  • I taught Digital Systems (ET1 622TN)

Students

PhD students:

  • Geerten Verweij
  • Marco Barbone (Imperial College)
  • Remi Brandt (RUG)
  • Hamed Kenawy (RUG)
  • Filip Yankov (RUG)
  • Maedeh Daryanavard Chounchenani (RUG)
  • Nima Esmi Rudbardeh (RUG)

PhD Alumni/ae:

  • Christos Strydis, Universal Processor Architecture for Biomedical Implants: The SiMS Project, March 2011
    External Examiners: Yale Patt, Alex Veidenbaum, Dirk De Ridder
    (first job: Post Doc at Erasmus Medical Center, the Netherlands)
  • Dimitris Theodoropoulos, Custom Architecture for Immersive-audio Applications (with Georgi Kuzmanov), May 2011
    External Examiners: Walid Najjar, Dionissis Pnevmatikatos, Edoardo Charbon
    (first job: Post Doc at Technical University of Crete, Greece)
  • Thomas Marconi, Efficient Runtime Management of Reconfigurable Hardware Resources, June 2011
    External Examiners: Walid Najjar, Jarmo Takala, Dionissis Pnevmatikatos
    (first job: Post Doc at the National University of Singapore (NUS), Singapore)
  • Daniele Ludovici, Technology Aware Network-on-Chip Connectivity and Synchronization Design (with Davide Bertozzi), June 2011
    External Examiners: Luigi Carro, Dionissis Pnevmatikatos, Gerard Smit
    (first job: Post Doc at the University of Ferrara, Italy)
  • Yi Lu, Realistic Online Resource Management for Partially Reconfigurable Systems, July 2011
    External Examiners: Apostolos Dollas, Neil Bergmann, Lars Svensson
    (first job: Researcher at ASML, the Netherlands)
  • Chunyang Gou, Customizable Memory Schemes for Data Parallel Accelerators, September 2011
    External Examiners: Andre Seznec, Per Stenstrom, Jarmo Takala
    (first job: PostDoc at TU Delft, the Netherlands)
  • Sebastian Isaza, Multicore Architectures for Bioinformatics Applications, October 2011
    External Examiners: Nikitas Dimopoulos, Alex Ramirez, Holger Blume
    (first job: PostDoc at Erasmus Medical Center, the Netherlands)
  • Catalin Ciobanu, Customizable Register Files for Multidimensional SIMD Architectures (with Georgi Kuzmanov), 3 March 2013
    External Examiners: Yale Patt, Peter Hofstee, Per Stenstrom
    (first job: PostDoc at Chalmers University of Technology, Sweden)
  • Rouzbeh Amini, Wireless Communication onboard Spacecraft (co-supervised with Eberhard Gil from Aerospace Engineering), 6 September 2016
    External Examiners: Alex Veidenbaum, M.H.G. Verhaegen, D.G. Simons, J. Leijtens
    (first job: European Space Agency, the Netherlands)
  • Ghazaleh Nazarian, Compiler Assisted Reliability Optimizations, 15 February 2019
    External Examiners: Luigi Carro, A. Shahbahrami, J.H.M. Frijns
    (first job: BrightSpace, the Netherlands)

Current MSc students:

  • Jun He
  • Panagiotis Afratis
  • Robert van Spijk
  • Gerard Aalberts

MSc Alumni/ae:

  1. Jing Cao, Power Efficient Digital Correlator in the scope of an UWB baseband design, October 2012
  2. S. Geursen, Reordering DRAM Requests for Improved Bandwidth Utilization, Jan 2012
  3. Y Okmen, SIMD Floating Point Extensions for Ray Tracing, November 2011
  4. V. Viswanathan, Hardware Support for Dynamic Partial Reconfiguration, Sept 2011A.
  5. Nandy, System Level Support for Dynamic Partial Reconfiguration, Sept 2011
  6. A. Jalaludeen, Multi-input Embedded Real-time Software Defined Radio, August 2011
  7. G. Cincerin, Free viewpoint 3D TV rendering platform, August 2011
  8. M. Beekema, Fault-Tolerant Platform for Intra-Spacecraft Modular Wireless Sensor 
Network, June 2011
  9. D. Siskos, A Co-processor for a Secure Implantable Medical Device, March 2011
  10. S. Keyser, Modular RT-Motion USB, February 2011
  11. A. Brandon, General Purpose Computing with Reconfigurable Acceleration, October 
2010
  12. D.P Riemens, Exploring suitable Adder Designs for Biomedical Implants, October 2010A.
  13. Abi Khaled, Congestion Management with Feedback Queue, September 2010
  14. A Piplani, Stereoscopic Remote Vision System, August 2010
  15. S Tzilis, Fine-Grain Runtime Fault Diagnosis for Reconfigurable Logic Blocks, June 
2010
  16. D. Stafylarakis, Security in RFID systems, May 2010
  17. A. Noroozi, Evaluation Methodology and Systematic Selection of Microcontrollers for 
Delfi-n3Xt Nanosatellite, May 2010
  18. D. Dave, Automated Implant Processor Design, May 2010
  19. M Berkhoff, Analysis and Implementation of the H.264 CABAC entropy decoding engine, 
March 2010
  20. E Gabdulkhakov, Performance analysis of SCISM organization applied to the IA-32 
architecture, January 2010
  21. M. Abikhaled, Code Integrity Check targeted on RISC, September 2009
  22. M. Roumi, Implementing Texture Feature Extraction Algorithms on FPGA, August 2009
  23. N.E. Cornejo, Fault Detection for the Delfi Nanosatellite Programme, July 2009 (summa 
cum laude)
  24. D. Hartanto, Reliable Ground Segment Data Handling System for Delfi-n3Xt Satellite 
Mission, pp. 207, Delft, The Netherlands, July 2009
  25. G. Stefanakis, Design and Implementation of a Range Trie for Address Lookup, July 
2009 (summa cum laude)
  26. F. Lemmel, The Brandaris128 Camera, June 2009
  27. R. de Smet, Range Trie Heuristics for Variable-Size Address Region Lookup, May 2009
  28. E. J. Houtgast, Scalability of Bioinformatics Applications for Multicore Architectures, 
November 2009
  29. K. Chandrasekar, Performance Validation of Networks on Chip, November 2009
  30. A. Arelakis, Efficient Pre-filtering Techniques for Packet Inspection, December 2008
  31. D. Zhu, Profiling Symmetric Encryption Algorithms for Implantable Medical Devices, 
December 2008
  32. U. Batool, Moving Critical Operations to Hardware Accelerators in Bioinformatic 
Applications, (visiting MSc student from University of Karlsruhe), December 2008
  33. A van den Berg, Automation of wrapper design for the reuse of a bus, network-on-chip, 
or other functional interconnect as test access mechanism in a chip, November 2007
  34. S. Umrani, Communication-centric Debugging of Systems on Chip using Networks on 
Chip, August 2007
  35. J. Hofman, Speeding up MPEG-4 colorspace conversion, April 2007
  36. CB Ciobanu, Customizing Vector Instruction Set Architectures, April 2007
  37. B. Spinean, Design Considerations For High Performance Vector Microarchitecture, April 2007
  38. P. Ren, Wrapper design for the reuse of a NoC or other functional interconnect as test infrastructure, December 2006
  39. N.T. Quach, Real-time Sky-detection Implementation, September 2006
  40. J. H. Bonarius, Low Power Techniques for Computer Architectures, August 2006
  41. M. Imran, Using COTS components in space applications, August 2006
  42. F. J. Bouwens, Power and Performance Optimization for ADRES, August 2006
  43. C. Strydis, Implantable microelectronic devices, (summa cum laude), July 2005
  44. D. Vermoen, Reverse engineering of Java Card applets using power analysis, June 2006
  45. B.G.C. de Ruijsscher, FPGA based accelerator for real-time skin segmentation, June 
2006
  46. V. van Adrighem, Tiny Linux kernel for minimalistic embedded systems, April 2006
  47. H. J. Visser, Minimalistic Platform for Linux Enabled Embedded Systems, April 2006
  48. G. de Goede, Accelerating the XviD IDCT on DAMP, (summa cum laude), January 2005
  49. M. P. Mul, PDP8 meets USB, August 2004
  50. R. Ashruf, The AES targeted on the MOLEN processor, July 2004
  51. J.A. van der Wijdeven, The Delfi-1 Command and Data Handling System, (co- advised 
with Wim Jongkind from L&R) July 2004
  52. J. van de Pol, USB-enabled PDP8 computer, June 2004
  53. J. Van der Vegt, Simulator-based exploration of the memory hierarchy for data 
dominated applications, May 2004
  54. W. Zwart, TR-DAMP: Testing and redesigning the Delft Altera-based Multimedia 
Platform, October 2004
  55. J. Eilers, DAMP: Design of the Delft Altera-based Multimedia Platform, October 2004
  56. D. Bao Linh, Vectorization of Digital Filters for CVP, July 2003