Said Hamdioui

I have been working on two main research lines: Dependability and Emerging Computing paradigms based on emerging device technologies.

Dependability

I have been working on different aspects related to dependability while collaborating with many universities and companies.

• Testability: This includes understanding the weaknesses of new technology nodes and integration, develop appropriate schemes that can enhance the outgoing product quality and reduce the cost. I have been strongly collaborating with companies such as NXP, IMEC, Qualcomm, Cadence, etc. as well as with universities such as Polito Di Torino.
• Reliability: This includes the analysis of reliability failure mechanism on the chip life time and failure rate, developing prediction models, design-for-reliability and mitigation schemes, etc. I have established a structural collaboration with IMEC on this topic; IMEC is one of the leading companies in the world when it comes to analyzing reliability of cutting edge technologies. In addition, I have a bilateral project with ESA (European Space Agency) on this topic. Collaboration has also been taking place with NXP and Karlsruhe Institute of Technology in Germany.
• Hardware Security: This includes Physical Unclonable Functions technology for strong security and authentication solutions, Development & design & of secure ICs, etc. I have been collaborating with Intrinsic ID (NL) on this topic as well as with LIRMM in France.

Emerging Computing paradigms

In addition to the above topics, I have started working on emerging computing paradigms using novel devices. In this context, I have developed a new architecture (CIM100X), based on Computation-In-Memory using memristor devices for data-intensive applications. All implementation aspects of such architecture are under investigation, including:

• Circuit design:

  in which logic and arithmetic operations are developed and designed based on resistive devices and by integrating the function within the crossbar memory.

• Architecture design: where different crossbar architectures are investigated while considering different metrics such as optimization of communication, power and control logic, as well as maximizing the parallelism and throughput.
• Compiler Level: in which a programming interface and the mapping of the parallel algorithms on the crossbar architecture are under study.
• Application level: in which applications and algorithms supporting massive parallelism are investigated in order to analyze their suitability for CIM100X architecture.

Teaching

Hamdioui teaches and/or contributes to the teaching of the following courses:

• ET3155: Algorithms and Data Structures, Bachelor course [see blackboard]

To solve a given e.g., electrical engineering (EE) problem, usually we start with developing an appropriate model of such a problem. Once the problem is modeled using an appropriate "Data Structure", one can focus one solving the modeled problem instead of the EE problem itself. Choosing the right "Data Structure" is therefore very important for generating efficient and optimal solutions. Solutions for such problems consist usually of "Algorithms". Analyzing the algorithms in terms of efficiency, time complexity, required memory, etc is therefore an important aspect when dealing with Electrical Engineering problems.

This course deals with the two important aspects of solving electrical engineering problems; namely "Data Structure" and "Algorithms". The most used data structure (e.g., stacks, trees, graphs, hash tables, matrices) will be addressed. The fundamentals from discrete mathematics that are needed to design and analyze algorithms such as complexity, counting methods, recurrence relations, etc. will be covered. Many standard algorithms (e.g., Dijkstra algorithm, Greedy algorithm) will be discussed and analyzed. NP-Complete problems will be also addressed.

• ET 3432: Computer Architecture and Organisation

This course provides an overview of the architecture and organization of a computer hardware system and the important principles of computer organization. The course demonstrates the interrelation between hardware and software, and illustrates how the computers operates and how they can be programmed, with the emphasis on processor design and implementation.

Topics discussed are Computer system overview, Measuring and comparing performance, ISA: instruction set architecture (MIPS, x86, 8051, JVM), Computer arithmetic, processor implementation, fast processor implementation, Memory hierarchy and caching, Interfacing, Modern architectures and organizations (superscalar,VLIW/IA64/Itanium), etc.

• ET 4174: System Programming in C [see blackboard]

The programming language C is a general-purpose programming language which features economy of expression, modern control flow and data structures, and a rich set of operators. C is not a "very high level" language, nor a "big" one, and is not specialized to any particular area of application. But its absence of restrictions and its generality make it more convenient and effective for many tasks like operating systems, compilers, etc.

This course provides the background needed to understand, modify, and extend an existing program (e.g., compilers). It also provides the necessary background to write programs for some applications. The topics discussed are: input and output, pointers and arrays, pointers to functions, structures, typedef, macro's, the C preprocessor, header files, type casting, etc. Other topics covered during the lab are: Makefiles, debugger, etc.

• ET4076: VLSI Test Technology and Reliability [see blackboard]

With the continuous scaling of transistor feature sizes, the VLSI chip density is exponentially increasing. This results in a significant complexity of today's and future VLSI technology; such a complexity has reached the point where billions of transistors are integrated on a single chip (as it is the case for System on Chip). To guarantee customer's satisfaction, produced VLSI chips have to be reliable and fully tested. Verification and production testing represent 50 to 60% of the chips production total cost, and are now the biggest cost of the technology. It has been known for a while that tackling problems associated with testing VLSI chips at earlier design stage levels significantly reduces the testing cost. Thus it is important for hardware designers to be exposed to concepts of VLSI testing which can help them design better products at lower cost. To get a feeling about how important is test technology, you can imagine that just (functionally) testing of a 64bit adder (no flips flops) at 1GHz will cost 585 years! What about today's chips with millions of flip flips? What are the practical and the efficient ways to deal with testing of VLSI chips?

This course is an introduction to the field of digital systems testing, which is an integral part of IC design and manufacturing. The topics discussed are: Importance of VLSI Testing, Test process and Automatic Test Equipment, Defects versus Fault Models, Fault Simulation, Logic Simulation, Combinational Circuit Testing, Sequential Circuit Testing, Memory Testing, Design-for-Testability, Scan Design, Boundary Scan, Built-in-Self Test, Delay Test, Current Testing, semiconductor and IC reliability, etc.

• ET4247: High Tech Startups [see blackboard]

The goal of this course is to make students familiar with the idea of setting up a company. We specifically focus on high tech products and markets because of their very specific dynamics.Students are expected to start a (virtual) company and to make a thorough analysis of the commercial possibilities of a particular product or technology. The students have to come up with an idea for the company themselves and should be as realistic as possible. The course will explain how to write business plans and make a financial analysis of the required investments. A number of speakers from industry (venture capitalists or entrepreneurs) will be invited to present their views.
The business plan will center around the following issues:
1. What is the target market and what are the unique selling points?
2. Who are the main competitors?
3. What are the required management skills?
4. What are the investment requirements?

Students

• PhD Students
  • Ongoing
    1. Innocent Agbo, Memory Reliability in Nano-Era: Modeling, Monitoring and Design.
    2. Du Nguyen Anh, Memristor based Computation-in-Memory (CIM) architecture for Big-Data.
    3. Lei Xie, Memristor Based Logic Circuit Design and Test .
    4. Adib Haron, Mapping Parallel Algorithms on Memristor-based Computation-in-Memory (CIM) architecture..
    5. Jintao Yu, Compiler and Simulation Plaform for Computation-in-Memory (CIM) Architecture.
    6. Daniel Kraak, Robust Memory Desigin-- Mitigation for aging.
•   Graduduated
  1. Mafalda Cortez, Reliability Assessment and Test Methods for Anti-counterfeiting Technology, November 2015.
  2. Motta Taouil, Yield and Cost Analysis for 3D Stacked ICs, Septmeber 2014. Graduated with Cum Laude. 
  3. Seyab Khan, Bias Temperature Instability Analysis, Monitoring and Mitigation for Nano-Scaled Circuits, September 2013. 
  4. Zaidi Haron, Testability and Fault Tolerance for Emerging Nanoelectronic Memories, May 2012.
•  Master Students
  •   Ongoing
    1. Haji Akhundov, Development and Design of Lightweight public-key crypto core, in collaboration with Intrinsic ID (the Netherlands). 
  •   Graduated
    1. Daniel Kraak, Experimental and Industrial Evaluation of Variability Resilient Schemes, in collaboration with NXP Eindhoven (the Netherlands). December 2015.
    2. Anteneh Gebregiorgis, Aging Mitigation Schemes for Embedded Memories, In collaboration with Karlsruhe Institute of Technology (KIT, Germany). July 2014
    3. Gijs Roelofs 'Design for Testability for Secure ICs', Master Thesis, CE-MS-2012-10, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven, the Netherlands, October 2013.
    4. Mahmoud Masadeh ’Interconnect Test for 3D Stacked Memories’, Master Thesis, CE-MS-2013-06, Delft University of Technology, the Netherlands, August 2013.
    5. Abiram Pattabiraman, Experimental Wind Flow Studies For Development and Calibration Of Thermal Models For Photovoltaic Cells, Delft University of Technology, in collaboration with IMEC (Belgium), July 2013.
    6. Christos Papameletis, 'Design-for-Testability Automation for 3D Stacked ICs', Master Thesis, CE-MS-2012-09, Delft University of Technology, in collaboration with IMEC (Belgium) and Cadence (USA), Augustus 2012.
    7. Subin Sivadas, 'Sensorless Algorithm development for Field Oriented Motor Control', Master Thesis, CE-MS-2011-04, Delft University of Technology, in collaboration with NXP Nijmegen (the Netherlands), November 2011.
    8. Vahid Roostaie, Design and analysts of a coherent memory subsystem for FPGA-based embeddedsystems, Master Thesis, CE-MS-2011-16, Delft University of Technology, in collaboration with Vec-torFabrics B.V. Eindhoven, The Netherlands, September 2011.
    9. Apurva Dargar, 'Modeling SRAM start-up characteristics for Physical Unclonable Functions', Maste Thesis, CE-MS-2011-11, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven,the Netherlands, July 2011. Graduated with Cum Laude.
    10. Venkataraman Krishnaswami, 'A New Test Paradigm for Semiconductor Memories in the Nano-Era', Master Thesis, CE-MS-2011-14, Delft University of Technology, July 2011.
    11. Vishwas Raj Jain, 'A Hierarchical Memory Diagnosis Approach: dealing with defects in all parts of the memory system', Master Thesis, CE-MS-2011-15, Delft University of Technology, July 2011. Graduated with Cum Laude.
    12. Nivesh Rai, 'Defect Oriented Testing for Analog/Mixed-Signal Devices', Master Thesis, CE-MS-2011-10, Delft University of Technology, in collaboration with NXP Semiconductors, Eindhoven, July 2011.
    13. Imran Achraf, 'MePoEfAr: Memory and Power Efficient Architecture for EmbeddedMicrocontrollers', Master Thesis, CE-MS-2011-17, Delft University of Technology, July 2011.
    14. Halil Kukner, 'Generic and Orthogonal March Element based Memory BIST Engine' Master Thesis, CE-MS-2010-25, Delft University of Technology, September 2010.
    15. Jouke Verbree, 'On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture', Master Thesis, CE-MS-2010-xx, Delft University of Technology, in collaboration with IMEC, Belgium, July 2010.
    16. Zaiyan Ahyadi, 'Experimental Analysis on ECC Schemes for Fault Tolerant Hybrid Memories', Master Thesis, CE-MS-2009-xx, Delft University of Technology, November 2009.
    17. Ghazaleh Nazarian, 'On-Line Testing for Routers in Networks on Chip', Master Thesis, CE-MS-2008-xx, Delft university of Technology, December 2008.
    18. Fomin Nkengafeh Anne, 'Experimental Analysis of Design-For-Testability Techniques in SRAMs', Master Thesis, CE-MS-2008-xx, Delft university of Technology, October 2008.
    19. Li Chuanyou, 'Testing Deep-submicron Embedded Memories in FPGAs', Master Thesis, CE-MS-2008-xx, Delft University of Technology in collaboration with Altera, San Jose, CA, USA, August 2008.