Stefan Wong

Currently, I am working within two research themes in the Computer Engineering laboratory. Within the MOLEN research theme, I am working on the micro-architecture of the MOLEN polymorphic processor (co-founder). Furthermore, I am developing an open-source paramterized and reconfigurable VLIW processor. This work is funded by the EU (the ERA project, coordinator) and is performed in close collaboration with several EU universities and companies. Within the ARACHNE research theme, I am working on network processing, collaborative grid computing. Currently, I am working on a new computing paradigm that combines modifiable firmware (microcode) and reconfigurable hardware with hardwired hardware, such as general-purpose superscalar processor cores.

During my PhD studies, I have been involved in research in computer architectures and parallel processors. More specifically, my focus was on architectural multimedia extensions for all mainstream and currently available processors. In particular, I worked on identifying possible candidates suited for parallelization and acceleration in hardware. An additional focus of my research has been the performance evaluation of reconfiguration schemes for reconfigurable hardware intended to support multimedia operations. In this evaluation process, I worked with a cycle-precise simulator and modified it extensively to suit performance evaluation purposes. Furthermore, manually editing the multimedia benchmark code in order to support the reconfiguration schemes was part of the process. In this process, I have also been involved in the implementation phase of reconfigurable hardware by utilizing synthesis and verification software. For my Master thesis, I worked on simulation and development of routing algorithms for a network of parallel processors arranged in a 'clustered torus'-topology. The simulation framework allowed existing routing algorithms to be tested and has led to new algorithms.

Research Interests: Embedded Processors, Computer Architecture and Engineering, Chip Multiprocessors, Multithreading, Multimedia Processing and Processors, High-Performance Processing and Processors, Microprogramming, Reconfigurable Computing, Synthesis and Verification, Computer Design, Logic Design, Computer Aided Design, Parallel Processing, Interconnection Networks, Multimedia Benchmarking, Grid Computing, Collaborative and Distributed Computing.

Personal Collaborations (past and current)

Over the years, I have worked with many researchers. Here is a short lis

• Geoffrey Brown, Indiana University, USA
• Rainer Buchty, Universitat Karlsruhe, Germany
• Luigi Carro, UFRGS, Brazil
• Jose Delgado-Frias, Washington State Univevsity, USA
• Nikitas Dimopoulos, University of Vicioria, Canada
• Paraskevas Evripidou, University of Cyprus, Cyprus
• Reza Hassanpour, Cankaya University, Turkey
• Wolfgang Karl, Universitat Karlsruhe, Germany
• Walid Najjar, University of California Riverside, USA
• Andy Pimentel, University of Amsterdam, The Netherlands
• Todor Stefanov, Leiden University, The Nether1ands
• Mehmet Tolun, Cankaya University, Turkey
• Pedro Trancoso, University of Cyprus, Cyprus
• more coming...

Invited talks

• ADCOM Conference, India (2009)
• University of Rio de Janeiro, Brazil (2009)
• University of Sao Paolo, Brazil (2009)
• UFRGS, Brazil (2009) - EMICRO Symposium
• Linkoping University, Sweden (2009)
• Chinese University of Hong Kong, Hong Kong SAR (2008)
• Cankaya University, Turkey (2008)
• University of Cyprus, Cyprus (2006,2007)
• UFRGS, Brazil (2006) - EMICRO Symposium

Professional acitivities

Involvement in organizing the following conferences and workshop

• WRC 2011 (General Chair)
• SAMOS 2010 (Steering Committee member)
• WRC 2010 (Program Co-Chair)
• ICCD 2009 (Financial Chair)
• SAMOS Workshop 2009 (General Co-Chair) - also Special Session Chair
• ARCS 2009 (Program Co-Chair)
• SAMOS Workshop 2008 (Program Co-Chair) - also Financial Chair
• WRC 2008 (Publicity Chair)
• DTIS 2007 (Financial Chair)
• FPL 2007 (Financial Chair)
• SAMOS Symposium 2007 (Financial & Publicity Chair)
• SAMOS Workshop 2006 (General Co-Chair) - also Financial & Publicity Chair
• ICS 2006 (Proceedings Chair)
• ASAP 2005 (Financial Chair)

Editorships:

• Proceedings of the SAMOS Workshop 2008
• Journal of Systems Architecture (Volume 53, Issue 10, October 2007)
• Proceedings of the Symposium: "The Future of Computing" (2007)
• Proceedings of the SAMOS Workshop 2006

Involvement as PC member in the following conferences and workshops:

• 2010: 2PARMA, FCST, FPL, RAW, SDR, FtMC
• 2009: ARC, ARCS, CF2009, PacRim, ReConfig, SAMOS, SIPS
• 2008: ARC, ARCS, FPL, HipHaC, SAMOS
• 2007: ARC, FPL, SAMOS
• 2006: ARC, SAMOS

Over the years, I have reviewed papers for the following journals:

• ACM Transactions on Reconfigurable Technology and Systems
• EURASIP Journal of Embedded Systems
• Journal of Signal Processing Systems
• IEEE Transactions on CAD of Integrated Circuits and Systems (TCAD)
• IEEE Transactions on Computers (TC)
• IEEE Transactions on Parallel and Distributed Systems
• IEEE Transactions on Signal Processing

I am member of the following organizations and communities:

• Senior Member of the IEEE
• Member of the ACM
• Member of the Hipeac
• Treasurer of the foundation "Stichting ter bevordering van het vakgebied Computer Engineering"

Project Involvements (past and current)

• Artemisia (NL STW)
• DDM-CMP (Cyprus government grant)
• Hartes (EU FP6 IP)
• VISIONS (EU FP6 STREP)
• ERA (EU FP7 STREP) - coordinator
• LoreLei (EU Marie Curie)

MSc projects

The following lists possible MSc thesis projects: (more coming - check back regularly)

• Implement MOLEN co-processors: The MOLEN processor comprises a general-purpose processor with a reconfigurable hardware unit that functions as a co-processor to speed up the processing of special kernels of applications running on the general-purpose processor. In the past, we have worked on many multimedia and network processing related kernels. We would like to extend this set of accelerators to cover more applications. In this project, we will determine the most interesting application at the time and define a project to build dedicated MOLEN co-processors.
• Extend the functionality of the MOLEN prototype The MOLEN prototype is currently implemented on the Virtex II-Pro and Virtex4 platforms. However, it is still an ongoing project to further extend the project to make the prototype more functional and accessible. In this project, we will define the needed functionality we need to extend the protoype with and work to achieve it.
• Extending the ρ-VEX processor: The ρ-VEX processor can be stand-alone extensible VLIW processor or attached to the MOLEN as a co-processor. In either case, the ρ-VEX processor is still in its early stages and its functionality and performance needs to be further improved. (Check out this article for more details). In this project, we will define the precise work on how to improve the ρ-VEX processor and work to achieve this.
• Implement the MOLEN concept on an AMD Opteron-Hyper transport platform: Reconfigurable hardware in increasingly moving closer to the general-purpose processor and that is the reason why reconfigurable hardware nowadays can be found connected to the Hypertransport bus attaching it closely to the AMD Opteron processor. In this project, we will implement the MOLEN concepts on the Bypertransport.
• Implement grid computing hardware functionalities: In collaborative grid computing, many computing nodes work together to achieve a common goal (e.g., large-scale scientific computing). It is expected that these nodes will contain reconfigurable hardare as they are getting increasingly more performant. In this project, we will work on either specific application acceleration on reconfigurable grid nodes or design network-related hardware functionalities to improve communication between the reconfigurable collaborative computing nodes.
• Implement OS scheduling techniques for reconfigurable computing: (description coming)
• Investigate interruptible hardware on reconfigurable computing platforms: (description coming)
• Investigate dynamic VLIW code scheduling: (description coming)

Email me if you are interested. The descriptions are purposely broad so students are giving freedom to find interesting topics (software, hardware, or both combined) within the described projects to work on. NOTE: Guidance of students outside the TU Delft is not possible.

Teaching

Courses

I am currently teaching the following course

• Logic Design (ET1 410 - 1st year BSC EE)
• Digital Systems (TI 2720-A - 2nd year BSC CS)
• System Desing using HDL (ET4 272 - MSc CE)
• Computer Architecture - Special Topics (ET4 078 - MSc CE)

I taught or have been involved in developing the following courses or labs :

• Computer Architecture (2nd year BSc Physics)
• Embedded Systems (3rd year BSc)
• Mars Rover project (minor "Electrical Engineering for Constructing sciences")
• MP3 Project (introductory lab for 1st year BSc CS)
• EPO-2: (1st BSc EE project)

Committees

I am member of the following committee

• Member of the Onderdeel Commissie (started November 2011)
  In this commitee I am part of the portfolios: education and finances.

I was a member of the following committees:

• Chair of the Board of Studies Electrical Engineering (Dutch: Opleidingscommissie Elektrotechniek) till October 2011
• Member of the Board of Examiners Computer Engineering and Embedded Systems (Dutch: Examencommissie CEES) till October 2010

Other activities

• I acted as the (doctoral) contact person in our lab for MSc students who wanted to perform their thesis project in our lab.
• I acted as the liaison between companies and MSc students who wanted to do their thesis project in the industry.
• Grassroots - This is a university program targeting at improving the utilization of IT technologies in courses. I was awarded two projects in 2007. The first project focused on improving the participation of students during the course period by involving in the development of weekly question sets for other students to make. The weekly question sets regarded course material taught. The second project involved the utilization of a poll system to evaluate the (perceived) knowledge of students and quality of the lectures and course material.

MSc students

Students looking to do a MSc thesis project with me can take a look at the

Students

PhD students

The following PhD students are currently working under my supervision:

• Fakhar Anjam - (topic) Collaborative Distributed Computing
• Roya Choupani - (topic) Scalable Video Coding
• Muhammad Nadeem - (topic) Transcoding
• Muhammad Faisal Nadeem - (topic) Collaborative Distributed Computing
• Mahmood Ahmadi (expected 2010) - (topic) Bloom Filters and Network Processing
• Jae Young Hur (expected 2010) - (topic) Network-on-Chip

The following PhD students finished their studies under my supervision:

• Filipa Duarte (finished 2008) - A Cache-based Hardware Accelerator for Memory Data Movements (PDF)

The following PhD students were partially guided by me:

• Christopher Kachris (partial guidance, finished 2007) - Reconfigurable Network Processing Platforms (PDF)
• Julio Carlos Balzano de Mattos (sandwich student UFRGS, 1 year) - The MOLEN Femto-Java Engine (PDF)

MSc students

Students looking to do a MSc thesis project with me can take a look at the following list.

The following MSc students are currently working on their thesis projects under my supervision:

• Siebe Krijgsman - (topic) A Partial-Reconfigurable Audio Generation and Manipulation Application
• Martin Ramcharan - (topic) Image Spam Detection
• Roel Seedorf - (topic) Fingerprint Scanning Application on Reconfigurable Hardware
• Joaquin Marcos Mosquera Rodriguez (Erasmus student)
• Gloria Garcia Dosil (Erasmus student)

The following MSc students finished their thesis projects under my supervision: (1997's is my own :-))

2012

to be added soon

2011

to be added soon

2010

1. A.A.C. Brandon, General Purpose Computing with Reconfigurable Acceleration, Delft, November 2010, MSc Thesis (BibTeX)

2008

2. T. van As, ρ-VEX: A Reconfigurable and Extensible VLIW Processor, September 2008, MSc Thesis (BibTeX)
3. M. Moumen, QoS Support in Delivering Video data over the Internet, May 2008, MSc Thesis (BibTeX)

2007

4. S.D. Breijer, Memory organization of the Molen prototype, August 2007, CE-MS-2007-06, MSc Thesis (BibTeX)
5. S.J. Raaijmakers, Run-Time Partial Reconfiguration on the Virtex-II Pro, July 2007, MSc Thesis (BibTeX)
6. R.R Abrahams, FPGA Implementation and Simulation of Hybrid Type-III ARQ for UMTS, July 2007, MSc Thesis (BibTeX)
7. B. Regelink, Modular Embedded Platform Design for Physical Asset Management, December 2007, MSc Thesis (BibTeX)
8. S Shao, Video-Over IP implementation on a Field-Programmable Gate Array, October 2007, MSc Thesis (BibTeX)

2006

9. G. Savir, Scalable and Reconfigurable Digital Front-End for SDR Wideband Channelizer, September 2006, MSc Thesis (BibTeX)
10. E.P.M. van Diggele, Translation of SystemC to Synthezisable VHDL, July 2006, MSc Thesis (BibTeX)
11. M. van den Braak, Voice over IP implementation on a Field-Programmable Gate Array, June 2006, MSc Thesis (BibTeX)
12. D. Ludovici, Performance Analysis of RR and FQ Algorithms in Reconfigurable Routers, pp. 131, Delft, The Netherlands, December 2006, MSc Thesis (BibTeX)

2005

13. Y Zhao, Benchmarking and Profiling the RSVP Protocol, August 2005, MSc Thesis (BibTeX)

2004

14. J. Yin, Session Initiation Protocol Benchmark Suite, Delft University of technology, October 2004, MSc Thesis (BibTeX)

2003

15. W. Lu, Designing TCP/IP Functions In FPGAs, Delft, The Netherlands, August 2003, MSc Thesis (BibTeX)
16. A. Snirpunas, Mapping of Motion Estimation on a VLIW Processor Template, Delft, The Netherlands, July 2003, MSc Thesis (BibTeX)
17. Y. Wu, Benchmarking Real-Time Network Processing, Delft, The Netherlands, July 2003, MSc Thesis (BibTeX)
18. G. A. Fossung, Performance Evaluation of Adders on FPGAs, June 2003, MSc Thesis (BibTeX)

2002

19. G. Luo, Synthetic Microcode Benchmark Generation, September 2002, MSc Thesis (BibTeX)

1997

20. S. Wong, Simulation of the Clustered Torus, April 1997, MSc Thesis (BibTeX)