Quantum Integrated Circuits

Item 1 of 1

DC DAC

Description Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing
Technology Intel 22-nm CMOS
References L. Enthoven, J. van Staveren, J. Gong, M. Babaie and F. Sebastiano, "A 3V 15b 157μW Cryo-CMOS DAC for Multiplexed Spin-Qubit Biasing," 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, pp. 228-229. doi.org/10.1109/VLSITechnologyandCir46769.2022.9830309

La Meije

Description Cryo-CMOS SAR ADC
Technology TSMC 40-nm CMOS
References G. Kiene, A. G. Sreenivasulu, R. W. J. Overwater, M. Babaie and F. Sebastiano, "Cryogenic Comparator Characterization and Modeling for a Cryo-CMOS 7b 1-GSa/s SAR ADC," ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC), Milan, Italy, 2022, pp. 53-56. doi.org/10.1109/ESSCIRC55480.2022.9911474

PLL with Triple-Mode VCO

Description PLL with Triple-Mode VCO
Technology Intel 22-nm FinFET CMOS
References J. Gong, B. Patra, L. Enthoven, J. van Staveren, F. Sebastiano and M. Babaie, "A 0.049mm2 7.1-to-16.8GHz Dual-Core Triple-Mode VCO Achieving 200dB FOM in 22nm FinFET," 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 1-3, doi.org/10.1109/ISSCC42614.2022.9731752.

Cryo RX

Description Cryo-CMOS Receiver for Multiple Spin Qubit Readout
Technology TSMC 40-nm CMOS
References B. Prabowo et al., "13.3 A 6-to-8GHz 0.17mW/Qubit Cryo-CMOS Receiver for Multiple Spin Qubit Readout in 40nm CMOS Technology," 2021 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 212-214. doi.org/10.1109/ISSCC42613.2021.9365848

 

 

Cryo-CMOS PLL

Description Cryo-CMOS PLL
Technology TSMC 40-nm bulk CMOS
References J. Gong, E. Charbon, F. Sebastiano and M. Babaie, "A 2.7mW 45fsrms-Jitter Cryogenic Dynamic-Amplifier-Based PLL for Quantum Computing Applications," 2021 IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, USA, 2021, pp. 1-2, doi.org/10.1109/CICC51472.2021.9431541.
  J. Gong, E. Charbon, F. Sebastiano and M. Babaie, "A Cryo-CMOS PLL for Quantum Computing Applications," in IEEE Journal of Solid-State Circuits, doi.org/10.1109/JSSC.2022.3223629

Blisard

Description Cryo-CMOS SAR ADC
Technology TSMC 40-nm CMOS
References G. Kiene et al., "13.4 A 1GS/s 6-to-8b 0.5mW/Qubit Cryo-CMOS SAR ADC for Quantum Computing in 40nm CMOS," 2021 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021, pp. 214-216. doi.org/10.1109/ISSCC42613.2021.9365927

 

 

Giant Array

Description Characterization Array
Technology TSMC 40-nm bulk CMOS
References  

 

 

HorseRidge

Description Cryo-CMOS Controller for Frequency-Multiplexed Spin Qubits and Transmons
Technology Intel 22-nm CMOS
References

B. Patra et al., "19.1 A Scalable Cryo-CMOS 2-to-20GHz Digitally Intensive Controller for 4×32 Frequency Multiplexed Spin Qubits/Transmons in 22nm FinFET Technology for Quantum Computers," 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 304-306. doi.org/10.1109/ISSCC19947.2020.9063109
  J. P. G. Van Dijk et al., "A Scalable Cryo-CMOS Controller for the Wideband Frequency-Multiplexed Control of Spin Qubits and Transmons," in IEEE Journal of Solid-State Circuits, vol. 55, no. 11, pp. 2930-2946, Nov. 2020. doi.org/10.1109/JSSC.2020.3024678

Charge-Sampling PLL

Description Charge-Sampling PLL
Technology TSMC 40-nm bulk CMOS
References J. Gong, F. Sebastiano, E. Charbon and M. Babaie, "A 10-to-12 GHz 5 mW Charge-Sampling PLL Achieving 50 fsec RMS Jitter, -258.9 dB FOM and -65 dBc Reference Spur," 2020 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Los Angeles, CA, USA, 2020, pp. 15-18, doi.org/10.1109/RFIC49505.2020.9218380.
  J. Gong, E. Charbon, F. Sebastiano and M. Babaie, "A Low-Jitter and Low-Spur Charge-Sampling PLL," in IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 492-504, Feb. 2022, doi.org/10.1109/JSSC.2021.3105335.

Cryo-CMOS VCO

Description Cryo-CMOS VCO
Technology TSMC 40-nm bulk CMOS
References J. Gong, Y. Chen, F. Sebastiano, E. Charbon and M. Babaie, "19.3 A 200dB FoM 4-to-5GHz Cryogenic Oscillator with an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications," 2020 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 308-310, doi.org/10.1109/ISSCC19947.2020.9062913.
  J. Gong, Y. Chen, E. Charbon, F. Sebastiano and M. Babaie, "A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 12, pp. 4810-4822, Dec. 2022, doi.org/10.1109/TCSI.2022.3199997.

CoolRef

Description Voltage References for the Ultra-Wide Temperature Range from 4.2K to 300K
Technology TSMC 40-nm CMOS
References J. van Staveren et al., "Voltage References for the Ultra-Wide Temperature Range from 4.2K to 300K in 40-nm CMOS," ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, pp. 37-40, doi.org/10.1109/ESSCIRC.2019.8902861