Taouil is currently an Asistant Professor in the Computer Engineering (CE) Laboratory, Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Delft University of Technology (TU-Delft). His expertise is in hardware dependability and is also co-founder of Cognitive-IC, a start-up focusing on hardware dependability solutions.
Taouil received his Master of Science and Doctoral degree (with honors) from Delft University of Technology, Delft, the Netherlands, in 2009 and 2014, respectively. During his PhD, he developed 3D-COSTAR which has been awarded with Hipeach Technology Transfer Award in 2015. After his PhD, he has been working as a Post-Doctoral researcher at the Computer Engineering Lab of the same university until 2018 where he subsequently was appointed as an assistant professor. During this period, he has been collaborating with several academic and industrial and partners such as ESA (the Netherlands), IMEC (Belgium) etc. His research focuses on hardware dependability (i.e., reliability, testability, hardware security). Taouil published over 100 journal and conference papers in a variety of topics, with a total citations of 1573, h-index=22 and i10-index=48. He has reviewed articles for many major journals and conferences and received several best papers awards in a variety of topics. Taouil has been involved in teaching several courses such as VLSI Test Technology & Reliability, Algorithms and Data Structures, System Programming in C and developed a new course on hardware security. Furthermore, he has been involved in many professional activities such as organizing conferences and summer schools, where he took several positions such as Program Chair, Publication Chair, Web Chair, etc.
In the past recent years, my research has focused on hardware dependability.
Research on hardware dependability aims at developing appropriate solutions that can guarantee the manufactured chips/ hardware are reliable and trustworthy. This research is being performed in collaboration with many partners such as NXP (NL), IMEC (BE), Cadence (USA), Qualcomm (USA), European Space Agency (NL), Polito Di Torino (IT), Karlsruhe Institute of Technology (DE), Riscure (NL), Dutch Forensic Institute (NL), Intrinsic ID (NL), etc. The focus of this research is:
- Testability: This includes understanding the weaknesses of new technology nodes and integration, developing appropriate fault models and test solutions that can enhance the outgoing product quality and reduce the cost. A lot of attention in our research is given to memories both traditional as well as emerging ones.
- Reliability: This includes the analysis of reliability failure mechanisms and their impact on the chip life time and failure rate, developing prediction models, design-for-reliability and mitigation schemes, etc.
- Hardware Security: This part focuses on design for security, i.e., design and implement hardware countermeasures during the design stage in order to prevent attacks in the field. It includes Physical Unclonable Functions technology for strong security and authentication solutions, analysis of security weaknesses of hardware, countermeasures against side-channel attacks and fault injections, etc.
Some ongoing (selected) projects include:
- SunRISE (PENTA-2018e-17004-SunRISE 2019-2022)
- Purpose: Design HW accelerators for privacy preserving technologies (homomorphic encryption) supporting AI on edge devices.
- Collaborators: SandGrain B.V, NL; Ani
- FORMOBILE (EU project/ SU-FCT02 2019-2022 )
- Purpose: FORMOBILE focuses on the complete FORensic investigation chain targeting MOBILE devices, from mobile phones to court
- Collaborators: Netherlands Forensic Institute, NL;
Some previous (selected) projects include:
- RESCUE (EU project/ MSCA-ITN 2017-2021)
- Purpose: Enhance design of complex systems at the next generation nanoelectronics technologies by addressing the demanding and mutually dependent aspects of reliability, security and quality, as well as corresponding electronic design automation tools.
- Collaborators: Intrinsic Tallinn University of Technology, EE; BTU Cottbus-Senftenberg, DE; Politecnico di Torino, IT; Cadence Design Systems GmbH, DE; IROC Technologies, FR; Intrinsic-ID B.V., NL; IHP GmbH, DE.
- REMAP (National project with ESA - 2016)
- Purpose: The project aims at understating, characterizing and modelling different emerging reliability failure mechanisms, which are rising and becoming dominant with new generations of advanced DRAM technology nodes used in aerospace. In particular, the objectie are: a) Intensive characterization of different reliability failure mechanisms (including the emerging ones) on the reliability aspects; i.e., failure rates and life time for DRAM memories, b) Exploring the impact of other aspects such as technology scaling, temperature, process variations, Vdd variations, workload/application, etc., c) Development of accurate failure rate prediction models, d) Validation of the models using both simulation and experiments (measurements).
- Collaborators: European Space Agencey (NL).
Ongoing PhD Students
- Hanzhi Xun, Device-Aware Test for RRAM
- Sicong Yuan, Device-Aware Test for MRAM
- Guilherme Cardoso Medeiros, Testing Hard-to-detect faults in FinFET embedded memories.
- Moritz Fieback, Testing RRAMs manufacturing defects, fault Modes and test solutions;
- Shayesteh Masoumian, Reliability analysis of SRAM-based PUFs in nano era.
- Troya Cagil Koylu, Design for Security - Countermeasures against fault injection attacks.
- Abdullah Aljuffri, Design for Security - Countermeasures against side-channel attacks.
Past PhD Students
- Lizhou Wu, Testing STT-MRAM: manufacturing defects, fault Modes and test solutions; Graduted with Cum Laude, Feb 22, 2021. Winner McCluskey Best Doctoral Thesis Award at International Test Conference, Oct 2021.
- Daniel Kraak, Memory Reliability Analysis Framework: Modeling and Mitigation; Dec 14, 2020.
- Innocent Agbo, Reliability Modeling and Mitigation for Embedded Memories, June 2018. Winner EDAA Outstanding Disseration Award at "Design Automation and Test in Eurrope", March 2019.
Ongoing Master Students
Graduated Master Students (click here to open the theses)
- Mudit Saxena, Pre-Silicon Power Leakage Assessment Framework using Generative Adversarial Networks, Aug 23, 2021
- Ryan van Leenen, Hardware-Based Methods for Memory Acquisition: Analysis and Improvements, Aug 23, 2021
- L.J. Hamburger, BTI in SRAM: Mitigation for BTI ageing in SRAMs, Nov 25, 2020.
- Hans Okkerman, Embedded Memory Security: Securing the IoT from the hardware level, Nov 30, 2020.
- Pavan Talluri, Fault Classification and Vulnerability Analysis of Microprocessors, in collaboration with RISCURE (the Netherlands), Nov 4th, 2020
- Marc Zwalua, Thermal Side Channel Analysis, Oct 28, 2020.
- Nourdin Ait El Mehdi, Analyzing the Resilience of Modern Smartphones Against Fault Injection Attacks, collaboration with RISCURE (the Netherlands), June 14, 2019.
- M.L.J. van Beusekom, Circumventing Secure JTAG: A detailed plan of Attack, in collaboration with Netherlands Forensic Institute, June 13, 2019.
- Pradeep Venkatachalam, S-Net: A Neural Network Based Countermeasures for AES, Aug 30, 2019.
- Michael Mainemer Lang, Quality and Cost modeling for 3D Stacked ICs, in collaboration with IMEC (Belgium) April 2018.
- Abdullah Aljuffri, Exploring Deep Learning for Hardware Attacks, in collaboration with RISCURE (the Netherlands), April 2018.
- Moritz Fieback, DRAM Reliability: Aging Analysis and Reliability Prediction Model, in collaboration with European Space Agency (ESA, the Netherlands), Dec 2017.
- Daniel Kraak, Experimental and Industrial Evaluation of Variability Resilient Schemes, in collaboration with NXP Eindhoven (the Netherlands). December 2015.
- Mahmoud Masadeh ’Interconnect Test for 3D Stacked Memories’, Master Thesis, CE-MS-2013-06, Delft University of Technology, the Netherlands, August 2013.