Said Hamdioui


Hamdioui is currently Chair Professor on Dependable and Emerging Computer Technologies, Head of the Computer Engineering Laboratory (CE-Lab) of the Delft University of Technology, the Netherlands. He is also co-founder and CEO of Cognitive-IC, a start-up focusing on hardware dependability solutions. He was also Head of the Quantum and Computer Engineering department from May 2019 to August 2023.

Hamdioui received the MSEE and PhD degrees (both with honors) from TUDelft. Prior to joining TUDelft as a professor, Hamdioui spent over seven years within industry including Microprocessor Products Group at Intel Corporation (Califorina, USA), IP and Yield Group at Philips Semiconductors R&D (Crolles, France) and DSP design group at Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research focuses on two domains: emerging technologies and computing paradigms (including memristors for logic and storage, in-memory-computing, brain-inspired computing, low power HW architecture for edge AI, etc.), and hardware dependability (including Testability, Reliability, Hardware Security).  He is currently involved in different projects

Hamdioui owns two patents, has published one book and contributed to other two, and had co-authored over 250 conference and journal papers. He has consulted for, and/or has given many trainings at many semiconductor companies (such as NXP, Intel, ST Microelectronics, Altera, Atmel, Renesas, Huawei, …) in the area Test and Design-for-Test of digital integrated circuits, including memoy testing; he has collaborated with many industry/research partners (examples are Intel, IMEC, NXP, Intrinsic ID, DS2, ST Microelectronics, Cadence, Politic di Torino, etc) in the field of dependable nano-computing and emerging technologies. He is strongly involved in the international community as a member of organizing committees (e.g., general chair, program chair, etc) or a member of the technical program committees of the leading conferences. He delivered dozens of keynote speeches, distinguished lectures, and invited presentations and tutorial at major international forums/conferences/schools and at leading semiconductor companies. Hamdioui served as Associate Editor of IEEE Transactions on VLSI Systems VLSI (2015-2018), and he was on the editorial board of Microelectronic Reliability Journal (2019-2020) and of the Journal of Electronic Testing - Theory and Applications JETTA (2011-2019). He is current a member of Editorial Board of ACM Journal on Emerging Technologies in Computing Systems (2020-present) and of IEEE Design & Test (2013-present). He is also member of AENEAS/ENIAC Scientific Committee Council (AENEAS =Association for European NanoElectronics Activities) and a Senior member of the IEEE,

Hamdioui is the recipient of many international/national awards. E.g., he is the recipient of European Design Automation Association (EDAA) Outstanding Dissertation Award 2001 (for his work on memory test techniques that have a widespread proliferation in the chip design industry), the European Commission Components and Systems Innovation Award for most innovative H2020 project MNEMOSENE at European Forum for Electronic Components and Systems 2020, the 2015 and 2022 HiPEAC Technology Transfer Award. In addition, he received many Best Paper Awards and nominations at leading international conferences (e.g.,  Design Automation and Test in Europe DATE in 2020 and 2021, International test Conference 2021, IEEE Computer Society Annual Symposium on VLSI 2016, IEEE International Conference on Computer Design ICCD 2015, IEEE European Test Symposium in 2020 and 2021, etc.). He was appointed 2017 Teacher of the Year Award at the faculty of Electrical Engineering, Delft University of Technology, the Netherlands; Moreover, he was appointed as an IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2021-2022, and he is leading member of Cadence Academic Network on Dependability and Design-for-Testability, and he was nominated for The Young Academy of the Royal Netherlands Academy of Arts and Sciences (KNAW) in 2009.




I have been working on two main research lines: Emerging Computing paradigms based on emerging device technologies and Hardware Dependability.

Emerging Computing paradigms

The research on emerging computing paradigms targets the invention, design, prototyping and demonstration of disruptive computing accelerators/engines by making use of unique features of emerging devices such as memristors and spintronics, while mainly focusing on energy-constrained low-granularity computing for a wide range of edge applications, including AI, such as personalized healthcare, smart environments and drones.  Examples of topics include computation-in-memory, new hardware architectures of AI, neuromorphic computing, spin-wave computing, etc. we adapts a holistic approach in which it addresses the whole computing engine design stack. The research is being performed in many partners such as TU Eindhoven in the Netherlands, RWTH in Germany, IMEC in the Netherlands and Belgium, European Space Agency in the Netherlands, IBM in Switzerland and in USA, etc.

  • Micro-architecture and circuit design: in which dedicated accelerators are defined and designed; logic and arithmetic operations are developed and designed based on emerging devices.
  • Architecture design: where different specialized accelerator are integrated while considering different metrics such as optimization of communication, power and control logic, as well as maximizing the parallelism and throughput.
  • Compilers and mapping methods: in which a programming interface and the mapping of (parallel) algorithms on the developed architecture are under study.
  • Algorithms and application: in which applications and algorithms supporting massive parallelism are investigated in order to analyze their suitability for emerging computing paradigms/ architectures.

Hardware Dependability

Research on hardware dependability aims at developing appropriate solutions that can guarantee the manufactured chips/ hardware are reliable and trustworthy.  This research is being performed in collaboration with many partners such as NXP in the Netherlands, IMEC in Belgium, Cadence in USA, Qualcomm in USA, European Space Agency in the Netherlands, Polito Di Torino in Italy, Karlsruhe Institute of Technology in Germany, Rescure in The Netherlands, Netherlands Forensic Institute (NFI) in the Netherlands, etc. The focus of this research is:

  • Testability: This includes understanding the weaknesses of new technology nodes and integration, developing appropriate fault models and test solutions that can enhance the outgoing product quality and reduce the cost. A lot of attention in our research is given to memories both traditional as well as emerging ones.
  • Reliability: This includes the analysis of reliability failure mechanisms and their impact on the chip life time and failure rate, developing prediction models, design-for-reliability and mitigation schemes, etc.
  • Hardware Security: This includes Physical Unclonable Functions technology for strong security and authentication solutions, analysis of security weaknesses of hardware and development of design-forsecurity solutions and secure ICs, etc.


List of some selected/ ongoing projects:

  • Ferro4Edge: (EU project, Horizon Europe, CL4-2023-Digital-Emerging-01-11: Jan 1, 2024- Dec 31, 2027)
  • Purpose: Ferro4Edge (Scalable, ferroelectric based accelerators for energy efficient edge AI) aims at developing, designing and demonstrating ultra-low power, scalable edge accelerator for artificial intelligence incorporating a memory augmented neural network, based on low cost, high density, multi-level, Back End of Line (BEoL) integrated ferroelectric (FE) technology.
  • Collaborator:  CEA (FR)NamLab (DE), Ecole Centrale de Lyon (FR), STMIcroelectronics (FR), SYNSENSE AG (CH), Ferroelectric Memory Company (DE).
  • CONVOLVE (EU project, Horizon Europe, CL4-2021-Digital-Emerging-01: Sept 2022- Aug 2025)  
    • Purpose: CONVOLVE (Seamless design of Smart Edge Processors), empowered by a top EU consortium, aims at bringing EU in the lead for edge processor design, by improving energy-efficiency by 100x, a 10x faster design time, moving AI to the edge, while guaranteeing real-time safety and security.
    • Collaborators: TU Eindhiven (NL), KU Leuevn (BE/NL), Bosh (DE), NXP (DE), ETH Zurich (CH), Uni of Manchester (UK), Uni of Murcia (ES), Thales Alenia Sapce (ES),  ...
  • DAIS (EU project, ECSEL, May 2021- April 2024)  
    • Purpose: The DAIS project researches and delivers distributed artificial intelligent systems. Our role in the project is to develop, design and demonstrate new hardware architectures based on emerging devices for edge AI; the focus is energy efficiency and reliability. Concepts such as computation-in-memory using memristor devices, spiking neural networks, low power design, etc will be investigated
    • Collaborators: IMEC (BE/NL), NXP (NL), ...
  • CHIRON (EU project/ FETOPEN, May 2018- April 2022)
    • Purpose: CHIRON targets a ground-breaking proof of principle of the essential elements for hybrid spin wave–CMOS computing. CHIRON will fabricate basic logic gates, such as inverters and majority gates, demonstrate their operation, and assess their performance. CHIRON will also develop magnetoelectric and multiferroic nanoresonators, based on nanoscale bulk acoustic resonators, which bear promise for high energy efficiency and large output signal. 
    • Collaborators: IMEC (BE), CNRS (FR), FORTH (GR), Thales (FR), UNIKL (DE), UPSud (FR), Solmates (NL), IMT (RO).
  • MNEMOSENE (EU project/ ICT: 2017-2021)
    • Purpose: Purpose: The project aims at demonstrating a new computation-in-memory (CIM) architecture based on resistive devices together with its required programming flow and interface. The targets are: (a) Design of new (Non-Von Neumann) CIM architecture based on a memristive device technology, (b) Design and test of memristor based logic and memories, (c) design of efficient on-chip communication schemes for computation in memory architecture, (d) Development and design of new mapping method and framework for efficient compilation and mapping of parallel algorithms on CIM architecture. 
    • Collaborators: Eindhoven University of Technology, IMEC, ARM, IBM, RWTH-Aachen, ETHZ, INRIA.
  • RESCUE (EU project/ MSCA-ITN 2017-2021)
    • Purpose: Enhance design of complex systems at the next generation nanoelectronics technologies by addressing the demanding and mutually dependent aspects of reliabilitysecurity and quality, as well as corresponding electronic design automation tools.
    • Collaborators: Intrinsic Tallinn University of Technology, EE; BTU Cottbus-Senftenberg, DE; Politecnico di Torino, IT; Cadence Design Systems GmbH, DE; IROC Technologies, FR; Intrinsic-ID B.V., NL; IHP GmbH, DE. 
  • TRACE (EU Project/ CATRENE 2016-2019)
    • Purpose: The project aims at developing a method including processes and tools required for the upgrade and qualified transfer of standard consumer electronic (CE) semiconductor components and technologies to the automotive domain. The method will be generally applicable to identify required modifications and adaptations as well as final conditions for qualification of CE components, technologies and resultant integrated systems for functionally safe and reliable automotive applications.
    • Collaborators/ Partners: NXP(NL), Heliox (NL), Catena (NL), UNi of Siegen (DE), Bosch (DE), BMW (DE), Volkswagen (DE), ST (FR), etc.
  • REMAP (National peroject with ESA- 2016)
    • Purpose: The project aims at understating, characterizing and modelling different emerging reliability failure mechanisms, which are rising and becoming dominant with new generations of advanced DRAM technology nodes used in aerospace. In particular, the objectie are: a) Intensive characterization of different reliability failure mechanisms (including the emerging ones) on the reliability aspects; i.e., failure rates and life time for DRAM memories, b) Exploring the impact of other aspects such as technology scaling, temperature, process variations, Vdd variations, workload/application, etc., c) Development of accurate failure rate prediction models, d) Validation of the models using both simulation and experiments (measurements). 
    • Collaborators: Euorpean Space Agencey (NL).
  • TUTORIAL (EU project/ H2020-TWINN- 2015)
    • Purposeboost the scientific excellence and innovation capacity in the trans-disciplinary field of nanoelectronics based dependable cyber-physical systems (NBDCPS) of Tallinn University of Technology (TUT) and its high-quality Twinning partners. 
    • Collaborators/partners: Tallinn University of Technology (TUT), Politecnico di Torino (POLITO) and Deutsches Zentrum für Luft- und Raumfahrt (DLR).



  • Theofilos Spyrou 
  • Mahdi Zahedi

Ongoing PhD Students

  • Emerging Computing paradigms/ brain-inpired cmputing PhD Students
    • Lennart Paul Liong Landsmeer, Memristor based Cerebellum-circuitry emulation, in collaboration with EMC (Erasmus Medical Centre, Rotterdam, The Netherlands). 
    • Zacharia Rudge, Memristor based AI accelerators for aerospace applications, in collaboration with European Space Agency (ESA).
    • Yash Biyani, FeFET based edge AI accelerators. 
    • Asmae El Arrassi, SRAM based edge AI accelerators.
    • Sumit Diware, Computation-in-memory based microarchitecture for edge AI.
    • Abhairaj Singh, Microarchitecture implementations for memristor based computation-in-memory accelerators. 
  • Test and Relaibility PhD students
    • Sicong Yuan, Test and DfX for STT-MRAMs, in collaboration wiith IMEC. 
    • Hanzhi Xun, Test and DfX for RRAMs. 
  • Hardware Security PhD Students 
    • Shayesteh Masoumian, Reliability analysis of SRAM-based PUFs in nano era.
    • Abdullah Aljuffri, design of HW driven secure systems 

Graduduated PhD students

  1. Mahdi Zahedi, Computation-in-memory: from application-specfic to prgrammable designs, planned for Dec 22, 2023.
  2. Felipe Augusto da Silva , EDA tools and methodologies for reliable nanoelectronic systems, Sept 21, 2022.
  3. Moritz Fieback, Testing RRAMs and Computation-in-Memory Decvices, July 8, 2022. 
  4. Abdulqader Nael Nathmi Mahmoud, Spin Wave Based Circuit Design, June 14, 2022. 
  5. Guilherme Cardoso Medeiros, Test and Diagnosis of Hard-to-detect faults in FinFET SRAMs, June 10, 2022
  6. Lizhou Wu, Testing STT-MRAM: manufacturing defects, fault Modes and test solutions; Graduted with Cum Laude, Feb 22, 2021. Winner McCluskey Best Doctoral Thesis Award at International Test Conference, Oct 2021. 
  7. Jintao Yu, Computation-in-Memory: From Circuits to Compilers; Feb 5th, 2021. 
  8. Daniel Kraak, Memory Reliability Analysis Framework: Modeling and Mitigation; Dec 14, 2020.
  9. Prashant D. Joshi, Dependable Network Technologies, Oct 7, 2019.
  10. Haoang Anh Du Nguyen, Computation-in-Mmeory based on Memristive devices, Sept 13, 2019
  11. Innocent Agbo, Reliability Modeling and Mitigation for Embedded Memories, June 2018. Winner EDAA Outstanding Disseration Award at "Design Automation and Test in Eurrope", March 2019. 
  12. Lei Xie, Memristive devices for logic design and computing, Feb 2018. 
  13. Mafalda Cortez, Reliability Assessment and Test Methods for Anti-counterfeiting Technology, November 2015.
  14. Motta Taouil, Yield and Cost Analysis for 3D Stacked ICs, Septmeber 2014. Graduated with Cum Laude. 
  15. Seyab Khan, Bias Temperature Instability Analysis, Monitoring and Mitigation for Nano-Scaled Circuits, September 2013. 
  16. Zaidi Haron, Testability and Fault Tolerance for Emerging Nanoelectronic Memories, May 2012.

 Ongoing Master Students


  Graduated  Master Students

  1. Shubhendu Shrivastava, Stress Aware Quiescent Current Test Optimization, in collaboration with NXP,  Aug 24, 2021
  2. Mudit Saxena,  Pre-Silicon Power Leakage Assessment Framework using Generative Adversarial Networks, Aug 23, 2021
  3. Ryan van Leenen, Hardware-Based Methods for Memory Acquisition: Analysis and Improvements, Aug 23, 2021
  4. Artemis Zografou, RRAM-based fault-tolerant Binary Neural Networks, July 27, 2021
  5. Sudeshna Dash, Accurate & Energy efficient ECG Classification using RRAM based DNN Architecture, July 19, 2021.
  6. L.J. Hamburger, BTI in SRAM: Mitigation for BTI ageing in SRAMs, Nov 25, 2020.
  7. Hans Okkerman, Embedded Memory Security: Securing the IoT from the hardware level, Nov 30, 2020.
  8. Pavan Talluri, Fault Classification and Vulnerability Analysis of Microprocessors, in collaboration with RISCURE (the Netherlands), Nov 4th, 2020
  9. Remon F. J. van Duijnen, ISA and Hardware Design for a Pipelined Computation-in-Memory tile, June 1st, 2020.
  10. Tijs Hol, Physical Defect Modling for RRAM, Aug 28, 2020.
  11. Marc Zwalua, Thermal Side Channel Analysis, Oct 28, 2020.
  12. Nourdin Ait El Mehdi, Analyzing the Resilience of Modern Smartphones Against Fault Injection Attacks, collaboration with RISCURE (the Netherlands), June 14, 2019.
  13. M.L.J. van Beusekom, Circumventing Secure JTAG: A detailed plan of Attack, in collaboration with Netherlands Forensic Institute, June 13, 2019.
  14. Abhairaj Singh, Circuit Design for Memristor Based In-Memory Computing, May 23, 2019
  15. Pradeep Venkatachalam, S-Net: A Neural Network Based Countermeasures for AES, Aug 30, 2019.
  16. Surya Nagarjan, Testing Computation-in-Memory Architectures Based on Emerging Memories, Nov 28, 2019.
  17. Santosh S. Malagi, Library Characterization for Cell-Aware Test, in collaboration with IMEC (Belgium), Sept 18, 2018.
  18. Michael Mainemer Lang, Quality and Cost modeling for 3D Stacked ICs, in collaboration with IMEC (Belgium) April 2018.
  19. Abdullah Aljuffri, Exploring Deep Learning for Hardware Attacks, in collaboration with RISCURE (the Netherlands), April 2018.
  20. Moritz Fieback, DRAM Reliability: Aging Analysis and Reliability Prediction Model, in collaboration with European Space Agency (ESA, the Netherlands), Dec 2017.  
  21. Haji Akhundov, Development and Design of Lightweight public-key crypto core, in collaboration with Intrinsic ID (the Netherlands), Jan 2017.  
  22. Daniel Kraak, Experimental and Industrial Evaluation of Variability Resilient Schemes, in collaboration with NXP Eindhoven (the Netherlands). December 2015.
  23. Anteneh Gebregiorgis, Aging Mitigation Schemes for Embedded Memories, In collaboration with Karlsruhe Institute of Technology (KIT, Germany). July 2014
  24. Gijs Roelofs 'Design for Testability for Secure ICs', Master Thesis, CE-MS-2012-10, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven, the Netherlands, October 2013.
  25. Mahmoud Masadeh ’Interconnect Test for 3D Stacked Memories’, Master Thesis, CE-MS-2013-06, Delft University of Technology, the Netherlands, August 2013.
  26. Abiram Pattabiraman, Experimental Wind Flow Studies For Development and Calibration Of Thermal Models For Photovoltaic Cells, Delft University of Technology, in collaboration with IMEC (Belgium), July 2013.
  27. Christos Papameletis, 'Design-for-Testability Automation for 3D Stacked ICs', Master Thesis, CE-MS-2012-09, Delft University of Technology, in collaboration with IMEC (Belgium) and Cadence (USA), Augustus 2012.
  28. Subin Sivadas, 'Sensorless Algorithm development for Field Oriented Motor Control', Master Thesis, CE-MS-2011-04, Delft University of Technology, in collaboration with NXP Nijmegen (the Netherlands), November 2011.
  29. Vahid Roostaie, Design and analysts of a coherent memory subsystem for FPGA-based embeddedsystems, Master Thesis, CE-MS-2011-16, Delft University of Technology, in collaboration with Vec-torFabrics B.V. Eindhoven, The Netherlands, September 2011.
  30. Apurva Dargar, 'Modeling SRAM start-up characteristics for Physical Unclonable Functions', Maste Thesis, CE-MS-2011-11, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven,the Netherlands, July 2011. Graduated with Cum Laude.
  31. Venkataraman Krishnaswami, 'A New Test Paradigm for Semiconductor Memories in the Nano-Era', Master Thesis, CE-MS-2011-14, Delft University of Technology, July 2011.
  32. Vishwas Raj Jain, 'A Hierarchical Memory Diagnosis Approach: dealing with defects in all parts of the memory system', Master Thesis, CE-MS-2011-15, Delft University of Technology, July 2011. Graduated with Cum Laude.
  33. Nivesh Rai, 'Defect Oriented Testing for Analog/Mixed-Signal Devices', Master Thesis, CE-MS-2011-10, Delft University of Technology, in collaboration with NXP Semiconductors, Eindhoven, July 2011.
  34. Imran Achraf, 'MePoEfAr: Memory and Power Efficient Architecture for EmbeddedMicrocontrollers', Master Thesis, CE-MS-2011-17, Delft University of Technology, July 2011.
  35. Halil Kukner, 'Generic and Orthogonal March Element based Memory BIST Engine' Master Thesis, CE-MS-2010-25, Delft University of Technology, September 2010.
  36. Jouke Verbree, 'On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture', Master Thesis, CE-MS-2010-xx, Delft University of Technology, in collaboration with IMEC, Belgium, July 2010.
  37. Zaiyan Ahyadi, 'Experimental Analysis on ECC Schemes for Fault Tolerant Hybrid Memories', Master Thesis, CE-MS-2009-xx, Delft University of Technology, November 2009.
  38. Ghazaleh Nazarian, 'On-Line Testing for Routers in Networks on Chip', Master Thesis, CE-MS-2008-xx, Delft university of Technology, December 2008.
  39. Fomin Nkengafeh Anne, 'Experimental Analysis of Design-For-Testability Techniques in SRAMs', Master Thesis, CE-MS-2008-xx, Delft university of Technology, October 2008.
  40. Li Chuanyou, 'Testing Deep-submicron Embedded Memories in FPGAs', Master Thesis, CE-MS-2008-xx, Delft University of Technology in collaboration with Altera, San Jose, CA, USA, August 2008.



Honors, Awards, Nominations and Appointments  (selected)

2023 Best Paper Award at HiPEAC (High Performance Embedded Architecture and Compilation) conference, Jan 16-18, Toulouse. Paper Title: Energy-efficient In-Memory Address Calculation
2023  HiPEAC Technology Transfer Award 2022, Jan 16-18, Toulouse. Topic: Device-aware testing: The road towards one defective part per billion
2022 2021 JETTA-TTTC Best Paper Award (JETTA= Journal of Electrical Testing: Theory and Applications). Paper Title: Evaluation of Single Event Upset Susceptibility of FinFETbased SRAMs with Weak Resistive Defects

Best Paper Award at IEEE European Test Symposium, May 22-26, Barcelona. Paper Title: Intermittent Undefined State Fault in RRAMs


Best Tech Idea of the Netherlands; Read more here.

2021 Appointed IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2021-2022.
2020 European Commission Components and Systems Innovation Award for most innovative H2020 project MNEMOSENE, at European Forum for Electronic Components and Systems, EFECS, Nov 25-26, 2020; see short presentation and ceremony

Distinguished Paper and Nomination for Best Paper Award at IEEE International Test Conference (ITC), Washington, DC, USA, Nov.  2020. Paper Title: Characterization, modeling and test of synthetic anti-ferromagnet flip defect in STT-MRAMs

2020 Best Paper Award at Design Automation and Test in Europe, DATE, D track, Grenoble, France, March 2020. Paper Title:  Impact of magnetic coupling and density on STT-MRAM performance.
2019 Nomination for Best Paper Award at IEEE European Test Symposium, May 27-31, Baden-Baden, Germany. Paper title: "Testing Scouting Logic-Based Computation-in-Memory Architectures".
2018 Best Paper Award at IEEE Latin American Test Symposium (LATS), Sao Paolo, Brazil, 12th - 16th March 2018. Paper Title:  "Ionizing radiation modeling in dram transistors,
2017 Best Paper Award at the International Conference on Frontier of Computer Science and Technology (FCST-2017), Exeter, UK, June 21-23, 2017.
2017 Teacher of the Year Award at the faculty of Electrical Engineering, Delft University of Technology, the Netherlands.
2016 Nominated for Outstanding Paper Award at International Conference on High Performance Computing & Simulation (HPCS), Innsbruck, Austria, July 18-22, Paper title: Parallel Matrix Multiplication on Memristor-Based Computation-in-Memory Architecture.
2016 Best Paper Award at IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, Pennsylvania, USA, July 11-13. Paper title:  "Quantification of Sense Amplifier Offset Voltage Degradation due to Zero- and Run-time Variability",
2016 HiPEAC Technology Transfer Award 2015, Jan 18-20, 2016, Prague, Czech Republic. Topic: 3D-COSTAR: A Tool to Optimize Test Flows of 3D Stacked Integrated Circuits. 
2015 Best Paper Award at 33rd IEEE International Conference on Computer Design (ICCD), October 18-21, New York, USA, Paper title: "Fast Boolean Logic Mapped on Memristor Crossbar".