Said Hamdioui


Hamdioui is currently Chair Professor on Dependable and Emerging Computer Technologies, Head of the Quantum and Computer Engineering department, and also serving as Head of the Computer Engineering Laboratory (CE-Lab) of the Delft University of Technology, the Netherlands. He is also co-founder and CEO of Cognitive-IC, a start-up focusing on hardware dependability solutions.

Hamdioui received the MSEE and PhD degrees (both with honors) from TUDelft. Prior to joining TUDelft as a professor, Hamdioui spent about seven years within industry including Microprocessor Products Group at Intel Corporation (Califorina, USA), IP and Yield Group at Philips Semiconductors R&D (Crolles, France) and DSP design group at Philips/ NXP Semiconductors (Nijmegen, The Netherlands). His research focuses on two domains: emerging technologies and computing paradigms (including memristors for logic and storage, in-memory-computing, neuromorphic computing, low power HW architecture for edge AI, etc.), and hardware dependability (including Testability, Reliability, Hardware Security).  He is currently involved in different projects

Hamdioui owns two patents, has published one book and contributed to other two, and had co-authored over 200 conference and journal papers. He has consulted for many companies (such as Intel, ST, Altera, Atmel, Renesas, …) in the area of memory testing and has collaborated with many industry/research partners (examples are Intel, IMEC, NXP, Intrinsic ID, DS2, ST Microelectronics, Cadence, Politic di Torino, etc) in the field of dependable nano-computing and emerging technologies. He is strongly involved in the international community as a member of organizing committees (e.g., general chair, program chair, etc) or a member of the technical program committees of the leading conferences. He delivered dozens of keynote speeches, distinguished lectures, and invited presentations and tutorial at major international forums/conferences/schools and at leading semiconductor companies. Hamdioui is a Senior member of the IEEE, Associate Editor of IEEE Transactions on VLSI Systems (TVLSI), and he serves on the editorial board of IEEE Design & Test, Elsevier Microelectronic Reliability Journal, and of the Journal of Electronic Testing: Theory and Applications (JETTA). He is also member of AENEAS/ENIAC Scientific Committee Council (AENEAS =Association for European NanoElectronics Activities).

Hamdioui is the recipient of many international/national awards. E.g., he  is the recipient of European Design Automation Association Outstanding Dissertation Award 2001; Best Paper Award at the International Conference on Frontier of Computer Science and Technology FCST-2017; Teacher of the Year Award at the faculty of Electrical Engineering, Delft University of Technology, the Netherlands; Best Paper Award at IEEE Computer Society Annual Symposium on VLSI (IVLSI) 2016; the 2015 HiPEAC Technology Transfer Award, Best Paper Award at 33rd IEEE International Conference on Computer Design ICCD 2015, Best paper Award at International conference on Design and Test of Integrated Systems in the nano-era DTIS 2011, IEEE Nano and Nano Korea award at IEEE NANO 2010, Intel informal Award for developed test methods for embedded caches in Itanuim processors. In addition, he is a leading member of Cadence Academic Network on Dependability and Design-for-Testability, and he was nominated for The Young Academy of the Royal Netherlands Academy of Arts and Sciences (KNAW) in 2009.



I have been working on two main research lines: Dependability and Emerging Computing paradigms based on emerging device technologies.

  • Dependability
    • I have been working on different aspects related to dependability while collaborating with many universities and companies. 
    • Testability: This includes understanding the weaknesses of new technology nodes and integration, develop appropriate schemes that can enhance the outgoing product quality and reduce the cost. I have been strongly collaborating with companies such as NXP, IMEC, Qualcomm, Cadence, etc. as well as with universities such as Polito Di Torino. 
    • Reliability: This includes the analysis of reliability failure mechanism on the chip life time and failure rate, developing prediction models, design-for-reliability and mitigation schemes, etc. I have established a structural collaboration with IMEC on this topic; IMEC is one of the leading companies in the world when it comes to analyzing reliability of cutting edge technologies. In addition, I have a bilateral project with ESA (European Space Agency) on this topic. Collaboration has also been taking place with NXP and Karlsruhe Institute of Technology in Germany. 
    • Hardware Security: This includes Physical Unclonable Functions technology for strong security and authentication solutions, Development & design & of secure ICs, etc. I have been collaborating with Intrinsic ID (NL) on this topic as well as with LIRMM in France.
      • Emerging Computing paradigms
        • In addition to the above topics, I have started working on emerging computing paradigms using novel devices. In this context, I have developed a new architecture (CIM100X), based on Computation-In-Memory using memristor devices for data-intensive applications. All implementation aspects of such architecture are under investigation, including:
        • Circuit design: in which logic and arithmetic operations are developed and designed based on resistive devices and by integrating the function within the crossbar memory.
        • Architecture design: where different crossbar architectures are investigated while considering different metrics such as optimization of communication, power and control logic, as well as maximizing the parallelism and throughput.
        • Compiler Level: in which a programming interface and the mapping of the parallel algorithms on the crossbar architecture are under study.
        • Application level: in which applications and algorithms supporting massive parallelism are investigated in order to analyze their suitability for CIM100X architecture.


List of some ongoing projects:

  • CHIRON (EU project/ FETOPEN)
    • Purpose: CHIRON targets a ground-breaking proof of principle of the essential elements for hybrid spin wave–CMOS computing. CHIRON will fabricate basic logic gates, such as inverters and majority gates, demonstrate their operation, and assess their performance. CHIRON will also develop magnetoelectric and multiferroic nanoresonators, based on nanoscale bulk acoustic resonators, which bear promise for high energy efficiency and large output signal. 
    • Collaborators: IMEC (BE), CNRS (FR), FORTH (GR), Thales (FR), UNIKL (DE), UPSud (FR), Solmates (NL), IMT (RO).
  • MNEMOSENE (EU project/ ICT 2017)
    • Purpose: Purpose: The project aims at demonstrating a new computation-in-memory (CIM) architecture based on resistive devices together with its required programming flow and interface. The targets are: (a) Design of new (Non-Von Neumann) CIM architecture based on a memristive device technology, (b) Design and test of memristor based logic and memories, (c) design of efficient on-chip communication schemes for computation in memory architecture, (d) Development and design of new mapping method and framework for efficient compilation and mapping of parallel algorithms on CIM architecture. 
    • Collaborators: Eindhoven University of Technology, IMEC, ARM, IBM, RWTH-Aachen, ETHZ, INRIA.
  • RESCUE (EU project/ MSCA-ITN 2017)
    • Purpose: Enhance design of complex systems at the next generation nanoelectronics technologies by addressing the demanding and mutually dependent aspects of reliabilitysecurity and quality, as well as corresponding electronic design automation tools.
    • Collaborators: Intrinsic Tallinn University of Technology, EE; BTU Cottbus-Senftenberg, DE; Politecnico di Torino, IT; Cadence Design Systems GmbH, DE; IROC Technologies, FR; Intrinsic-ID B.V., NL; IHP GmbH, DE. 
  • TRACE (EU Project/ CATRENE 2016)
    • Purpose: The project aims at developing a method including processes and tools required for the upgrade and qualified transfer of standard consumer electronic (CE) semiconductor components and technologies to the automotive domain. The method will be generally applicable to identify required modifications and adaptations as well as final conditions for qualification of CE components, technologies and resultant integrated systems for functionally safe and reliable automotive applications.
    • Collaborators/ Partners: NXP(NL), Heliox (NL), Catena (NL), UNi of Siegen (DE), Bosch (DE), BMW (DE), Volkswagen (DE), ST (FR), etc.
  • REMAP (National peroject with ESA- 2016)
    • Purpose: The project aims at understating, characterizing and modelling different emerging reliability failure mechanisms, which are rising and becoming dominant with new generations of advanced DRAM technology nodes used in aerospace. In particular, the objectie are: a) Intensive characterization of different reliability failure mechanisms (including the emerging ones) on the reliability aspects; i.e., failure rates and life time for DRAM memories, b) Exploring the impact of other aspects such as technology scaling, temperature, process variations, Vdd variations, workload/application, etc., c) Development of accurate failure rate prediction models, d) Validation of the models using both simulation and experiments (measurements). 
    • Collaborators: Euorpean Space Agencey (NL).
  • TUTORIAL (EU project/ H2020-TWINN- 2015)
    • Purposeboost the scientific excellence and innovation capacity in the trans-disciplinary field of nanoelectronics based dependable cyber-physical systems (NBDCPS) of Tallinn University of Technology (TUT) and its high-quality Twinning partners. 
    • Collaborators/partners: Tallinn University of Technology (TUT), Politecnico di Torino (POLITO) and Deutsches Zentrum für Luft- und Raumfahrt (DLR).


  • PostDocs
    • Cezar Wedig Reinbrecht 
  • PhD Students
    • Ongoing
      • Computation-in-Memory PhD Students
        • Du Nguyen Anh, Memristor based Computation-in-Memory (CIM) architecture for Big-Data.
        • Adib Haron, Mapping Parallel Algorithms on Memristor-based Computation-in-Memory (CIM) architecture..
        • Jintao Yu, Compiler and Simulation Plaform for Computation-in-Memory (CIM) Architecture
        • Muath Abu Lebdeh, Computation-in-Memory Circuit and Low Level Architecture and Modeling  
      • Test and Relaibility PhD students
        • Daniel Kraak, Robust Memory Desigin-- Mitigation for aging.
        • Prashant D. Joshi, Dependable Network Topologies 
        • Lizhou Wu, Fault Models, Test, DFT and BIST for STT-MRAMs.
        • Guilherme Cardoso Medeiros, Testing FinFET memories.
        • Felipe Augusto da Silva, EDA tools and methodologies for high quality nanoelectronic systems (in collaboration with Cadence)
      • Hardware Security PhD Students 
        • Haji Akhundov, Design for secure systems.
        • Troya Cagil Koylu, Design for Security.
        • Shayesteh Masoumian, Novel PUF Technology (in collaboration with Intrinsic ID)
        • Abdullah Aljuffri, design of HW driven secure systems 
      • Graduduated
        1. Innocent Agbo, Reliability Modeling and Mitigation for Embedded Memories, June 2018.
        2. Lei Xie, Memristive devices for logic design and computing, Feb 2018. 
        3. Mafalda Cortez, Reliability Assessment and Test Methods for Anti-counterfeiting Technology, November 2015.
        4. Motta Taouil, Yield and Cost Analysis for 3D Stacked ICs, Septmeber 2014. Graduated with Cum Laude. 
        5. Seyab Khan, Bias Temperature Instability Analysis, Monitoring and Mitigation for Nano-Scaled Circuits, September 2013. 
        6. Zaidi Haron, Testability and Fault Tolerance for Emerging Nanoelectronic Memories, May 2012.
  •  Master Students
    •   Ongoing
      1. Santosh S Malagi, Cell-Aware Test Library Characterization for Advanced Technology Nodes, in collaboration with IMEC (Belgium). 
    •   Graduated
      1. Michael Mainemer Lang, Quality and Cost modeling for 3D Stacked ICs, in collaboration with IMEC (Belgium) April 2018.
      2. Abdullah Aljuffri, Exploring Deep Learning for Hardware Attacks, in collaboration with RISCURE (the Netherlands), April 2018.
      3. Moritz Fieback, DRAM Reliability: Aging Analysis and Reliability Prediction Model, in collaboration with European Space Agency (ESA, the Netherlands), Dec 2017.  
      4. Haji Akhundov, Development and Design of Lightweight public-key crypto core, in collaboration with Intrinsic ID (the Netherlands), Jan 2017.  
      5. Daniel Kraak, Experimental and Industrial Evaluation of Variability Resilient Schemes, in collaboration with NXP Eindhoven (the Netherlands). December 2015.
      6. Anteneh Gebregiorgis, Aging Mitigation Schemes for Embedded Memories, In collaboration with Karlsruhe Institute of Technology (KIT, Germany). July 2014
      7. Gijs Roelofs 'Design for Testability for Secure ICs', Master Thesis, CE-MS-2012-10, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven, the Netherlands, October 2013.
      8. Mahmoud Masadeh ’Interconnect Test for 3D Stacked Memories’, Master Thesis, CE-MS-2013-06, Delft University of Technology, the Netherlands, August 2013.
      9. Abiram Pattabiraman, Experimental Wind Flow Studies For Development and Calibration Of Thermal Models For Photovoltaic Cells, Delft University of Technology, in collaboration with IMEC (Belgium), July 2013.
      10. Christos Papameletis, 'Design-for-Testability Automation for 3D Stacked ICs', Master Thesis, CE-MS-2012-09, Delft University of Technology, in collaboration with IMEC (Belgium) and Cadence (USA), Augustus 2012.
      11. Subin Sivadas, 'Sensorless Algorithm development for Field Oriented Motor Control', Master Thesis, CE-MS-2011-04, Delft University of Technology, in collaboration with NXP Nijmegen (the Netherlands), November 2011.
      12. Vahid Roostaie, Design and analysts of a coherent memory subsystem for FPGA-based embeddedsystems, Master Thesis, CE-MS-2011-16, Delft University of Technology, in collaboration with Vec-torFabrics B.V. Eindhoven, The Netherlands, September 2011.
      13. Apurva Dargar, 'Modeling SRAM start-up characteristics for Physical Unclonable Functions', Maste Thesis, CE-MS-2011-11, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven,the Netherlands, July 2011. Graduated with Cum Laude.
      14. Venkataraman Krishnaswami, 'A New Test Paradigm for Semiconductor Memories in the Nano-Era', Master Thesis, CE-MS-2011-14, Delft University of Technology, July 2011.
      15. Vishwas Raj Jain, 'A Hierarchical Memory Diagnosis Approach: dealing with defects in all parts of the memory system', Master Thesis, CE-MS-2011-15, Delft University of Technology, July 2011. Graduated with Cum Laude.
      16. Nivesh Rai, 'Defect Oriented Testing for Analog/Mixed-Signal Devices', Master Thesis, CE-MS-2011-10, Delft University of Technology, in collaboration with NXP Semiconductors, Eindhoven, July 2011.
      17. Imran Achraf, 'MePoEfAr: Memory and Power Efficient Architecture for EmbeddedMicrocontrollers', Master Thesis, CE-MS-2011-17, Delft University of Technology, July 2011.
      18. Halil Kukner, 'Generic and Orthogonal March Element based Memory BIST Engine' Master Thesis, CE-MS-2010-25, Delft University of Technology, September 2010.
      19. Jouke Verbree, 'On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture', Master Thesis, CE-MS-2010-xx, Delft University of Technology, in collaboration with IMEC, Belgium, July 2010.
      20. Zaiyan Ahyadi, 'Experimental Analysis on ECC Schemes for Fault Tolerant Hybrid Memories', Master Thesis, CE-MS-2009-xx, Delft University of Technology, November 2009.
      21. Ghazaleh Nazarian, 'On-Line Testing for Routers in Networks on Chip', Master Thesis, CE-MS-2008-xx, Delft university of Technology, December 2008.
      22. Fomin Nkengafeh Anne, 'Experimental Analysis of Design-For-Testability Techniques in SRAMs', Master Thesis, CE-MS-2008-xx, Delft university of Technology, October 2008.
      23. Li Chuanyou, 'Testing Deep-submicron Embedded Memories in FPGAs', Master Thesis, CE-MS-2008-xx, Delft University of Technology in collaboration with Altera, San Jose, CA, USA, August 2008.