Dr.ir. M.C.R. Fieback
Dr.ir. M.C.R. Fieback
Profiel
Moritz Fieback received his PhD degree from Delft University of Technology in the Netherlands in 2022. Currently, he is working as an assistant professor in the same university. His research interests include device and defect modeling, test and reliability of emerging memories, and computation-in-memory systems. He has co-authored over 40 articles and won 3 best paper awards.
Expertise
Publicaties
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2024
A DfT Strategy for Guaranteeing ReRAM’s Quality after Manufacturing
T. S. Copetti / M. Fieback / T. Gemmeke / S. Hamdioui / L. M.Bolzani Poehls
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2023
Characterization and Test of Intermittent Over RESET in RRAMs
Hanzhi Xun / Moritz Fieback / Sicong Yuan / Hassen Aziza / Mathijs Heidekamp / Thiago Copetti / Leticia Bolzani Poehls / Mottaqiallah Taouil / Said Hamdioui
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2023
Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs
Hanzhi Xun / Moritz Fieback / Sicong Yuan / Ziwei Zhang / Mottaqiallah Taouil / Said Hamdioui
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2023
Dependability of Future Edge-AI Processors
Pandora’s Box
Manil Dev Gomony / Anteneh Gebregiorgis / Moritz Fieback / Marc Geilen / Sander Stuijk / Jan Richter-Brockmann / Rajendra Bishnoi / Mottaqiallah Taouil / Said Hamdioui / More Authors -
2023
Device Aware Diagnosis for Unique Defects in STT-MRAMs
Ahmed Aouichi / Sicong Yuan / Moritz Fieback / Siddharth Rao / Woojin Kim / Erik Jan Marinissen / Sebastien Couet / Mottaqiallah Taouil / Said Hamdioui
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Prijzen
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2023
LATS 2022 Best Paper Award
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2022-5
ETS 2021 Best Paper Award
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2018
LATS 2018 Best Paper Award
Nevenwerkzaamheden
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2024-01-01 - 2025-12-31